Hardware/GX

Pixel Engine
Access
Broadway	Full
Starlet	None
Registers
Base	0x0c001000
Length	0x100
Access size	32 bits
Byte order	Big Endian
IRQs
Broadway	9,10

Command Processor
Access
Broadway	Full
Starlet	None
Registers
Base	0x0c000000
Length	0x80
Access size	16 bits
Byte order	Big Endian
IRQs
Broadway	11

GX FIFO

Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

BP (blitting processor) registers

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.

EFB source registers

One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:

• 0x49: coordinates to top left of rectangle in EFB that will be copied (packed format, unknown)
• 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)

XFB destination registers

The destination of the copy in the XFB is specified by the physical address of the XFB and the row stride (basically width of row, but no scaling appled).

• 0x4b: Address of destination (XFB). BEWARE: You only have 24 bits, which means your XFB must reside somewhere in the low 16MiB of RAM.
• 0x4d: Low 10 bits specify x coordinate of destination.

Copy control register

• 0x52: This register starts a copy. Important bits:

 * bit 11: Clear enable flag
 * bits 13-16: Set all to 1 to enable a copy.

Copy filter registers

Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.

Beginning a copy

The following must take place to do a copy:

• Setup clear and z clear registers (optional)
• Set source and destination registers
• Write to display copy control register to begin a copy
• Set clear, z, and control registers again (what? doubt necessary, libogc GX is stupid)

CP (command processor) registers

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.

XF (transform) registers

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.