Difference between revisions of "Hardware/GX"
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===BP registers=== | ===BP registers=== | ||
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bits of something. | The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bits of something. | ||
| − | ===CP registers=== | + | ===CP (command processor) registers=== |
The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. | The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. | ||
| − | ===XF registers=== | + | ===XF (transform) registers=== |
The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas. | The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas. | ||
Revision as of 03:37, 2 March 2009
| Pixel Engine | |
| Access | |
|---|---|
| Broadway | Full |
| Starlet | None |
| Registers | |
| Base | 0x0c001000 |
| Length | 0x100 |
| Access size | 32 bits |
| Byte order | Big Endian |
| IRQs | |
| Broadway | 9,10 |
| Command Processor | |
| Access | |
|---|---|
| Broadway | Full |
| Starlet | None |
| Registers | |
| Base | 0x0c000000 |
| Length | 0x80 |
| Access size | 16 bits |
| Byte order | Big Endian |
| IRQs | |
| Broadway | 11 |
| This Hardware-related article is a stub. You can help WiiBrew by expanding it. |
| This article may be improved with information from Yet Another GameCube Documentation. You can help WiiBrew by expanding this article with the information and wikifying it. |
GX FIFO
Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.
BP registers
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bits of something.
CP (command processor) registers
The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.
XF (transform) registers
The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.