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Difference between revisions of "Hardware/USB Host Controller"

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(New page: {{Infobox MMIO | title = EHCI | arm = Full | base = 0x0d040000 | len = 0x100 | bits = 32 | armirq = unknown{{check}} }} {{Infobox MMIO | title = OHCI #0 | arm = Full | base = 0x0d050000 | ...)
 
(add EHCI and OHCI registers (from 100J/121J))
 
(7 intermediate revisions by 4 users not shown)
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 +
= Enhanced Host Controller Interface (EHCI) =
 
{{Infobox MMIO
 
{{Infobox MMIO
 
| title = EHCI
 
| title = EHCI
Line 5: Line 6:
 
| len = 0x100
 
| len = 0x100
 
| bits = 32
 
| bits = 32
−
| armirq = unknown{{check}}
+
| hwdirq = 4
 +
| endian = revlittle
 
}}
 
}}
 +
 +
 +
 +
{{reglist|EHCI Registers}}
 +
{{rld|0x0d040000|32|EHC0_CAPLENVER||}}
 +
{{rld|0x0d040004|32|EHC0_HCSPARAMS||}}
 +
{{rld|0x0d040008|32|EHC0_HCCPARAMS||}}
 +
{{rld|0x0d04000c|32|EHC0_HCSP_PORTROUTE||}}
 +
{{rld|0x0d040010|32|EHC0_USBCMD||}}
 +
{{rld|0x0d040014|32|EHC0_USBSTS||}}
 +
{{rld|0x0d040018|32|EHC0_PRUSBINTR||}}
 +
{{rld|0x0d040018|32|EHC0_USBINTR||}}
 +
{{rld|0x0d04001c|32|EHC0_FRINDEX||}}
 +
{{rld|0x0d040020|32|EHC0_CTRLDSSEGMENT||}}
 +
{{rld|0x0d040024|32|EHC0_PERIODICLISTBASE||}}
 +
{{rld|0x0d040028|32|EHC0_ASYNCICLISTADDR||}}
 +
{{rld|0x0d040050|32|EHC0_PRCONFIGFLAG||}}
 +
{{rld|0x0d040054|32|EHC0_PORTSC||}}
 +
{{rld|0x0d040054|32|PORT_CTRL||}}
 +
{{rld|0x0d040090|32|EHC_MISC_CTRL0||}}
 +
{{rld|0x0d040094|32|EHC_PKTBUF_THRESHOLD||}}
 +
{{rld|0x0d040098|32|USB_PHY_STS0||}}
 +
{{rld|0x0d04009c|32|USB_PHY_STS1||}}
 +
{{rld|0x0d0400a0|32|USB_PHY_STS2||}}
 +
{{rld|0x0d0400a4|32|UTMI_CTRL||}}
 +
{{rld|0x0d0400a8|32|BIST_CTRL||}}
 +
{{rld|0x0d0400ac|32|EHC_MISC_CTRL1||}}
 +
{{rld|0x0d0400b0|32|USB_PHYCMN_CAL||}}
 +
{{rld|0x0d0400b4|32|PHYADJ_CTRL||}}
 +
{{rld|0x0d0400c4|32|EHC_PKTBUF_DEPTH||}}
 +
{{rld|0x0d0400c8|32|EHC_BREAK_MEM_XFR||}}
 +
{{rld|0x0d0400cc|32|USB_CHICKENBITS||}}
 +
|}
 +
 +
 +
= Open Host Controller Interface #0 =
 
{{Infobox MMIO
 
{{Infobox MMIO
−
| title = OHCI #0
+
| title = OHCI0
 
| arm = Full
 
| arm = Full
 
| base = 0x0d050000
 
| base = 0x0d050000
 
| len = 0x200
 
| len = 0x200
 
| bits = 32{{check}}
 
| bits = 32{{check}}
−
| armirq = unknown{{check}}
+
| hwdirq = 5
 +
| endian = revlittle
 
}}
 
}}
 +
 +
 +
 +
{{reglist|OHCI0 Registers}}
 +
{{rld|0x0d050000|32|OHC0_HCREV||}}
 +
{{rld|0x0d050004|32|OHC0_HCCTRL||}}
 +
{{rld|0x0d050008|32|OHC0_HCCMDSTAT||}}
 +
{{rld|0x0d05000c|32|OHC0_HCINTSTAT||}}
 +
{{rld|0x0d050010|32|OHC0_HCINTEN||}}
 +
{{rld|0x0d050014|32|OHC0_HCINTDIS||}}
 +
{{rld|0x0d050018|32|OHC0_HCHCCA||}}
 +
{{rld|0x0d05001c|32|OHC0_HCPERCUR||}}
 +
{{rld|0x0d050020|32|OHC0_HCCTRLHD||}}
 +
{{rld|0x0d050024|32|OHC0_HCCTRLCUR||}}
 +
{{rld|0x0d050028|32|OHC0_HCBLKHD||}}
 +
{{rld|0x0d05002c|32|OHC0_HCBLKCUR||}}
 +
{{rld|0x0d050030|32|OHC0_HCDNHD||}}
 +
{{rld|0x0d050034|32|OHC0_HCFMINT||}}
 +
{{rld|0x0d050038|32|OHC0_HCFMREM||}}
 +
{{rld|0x0d05003c|32|OHC0_HCFMNUM||}}
 +
{{rld|0x0d050040|32|OHC0_HCPERST||}}
 +
{{rld|0x0d050044|32|OHC0_HCLSTHRESH||}}
 +
{{rld|0x0d050048|32|OHC0_HCRHDESCA||}}
 +
{{rld|0x0d05004c|32|OHC0_HCRHDESCB||}}
 +
{{rld|0x0d050050|32|OHC0_HCRHSTAT||}}
 +
{{rld|0x0d050054|32|OHC0_HCRHPORT1STAT||}}
 +
{{rld|0x0d050058|32|OHC0_HCRHPORT2STAT||}}
 +
|}
 +
 +
 +
= Open Host Controller Interface #1 =
 
{{Infobox MMIO
 
{{Infobox MMIO
−
| title = OHCI #1
+
| title = OHCI1
 
| arm = Full
 
| arm = Full
 
| base = 0x0d060000
 
| base = 0x0d060000
 
| len = 0x200
 
| len = 0x200
 
| bits = 32{{check}}
 
| bits = 32{{check}}
−
| armirq = unknown{{check}}
+
| hwdirq = 6
 +
| endian = revlittle
 
}}
 
}}
 +
 +
 +
 +
{{reglist|OHCI1 Registers}}
 +
{{rld|0x0d060000|32|OHC1_HCREV||}}
 +
{{rld|0x0d060004|32|OHC1_HCCTRL||}}
 +
{{rld|0x0d060008|32|OHC1_HCCMDSTAT||}}
 +
{{rld|0x0d06000c|32|OHC1_HCINTSTAT||}}
 +
{{rld|0x0d060010|32|OHC1_HCINTEN||}}
 +
{{rld|0x0d060014|32|OHC1_HCINTDIS||}}
 +
{{rld|0x0d060018|32|OHC1_HCHCCA||}}
 +
{{rld|0x0d06001c|32|OHC1_HCPERCUR||}}
 +
{{rld|0x0d060020|32|OHC1_HCCTRLHD||}}
 +
{{rld|0x0d060024|32|OHC1_HCCTRLCUR||}}
 +
{{rld|0x0d060028|32|OHC1_HCBLKHD||}}
 +
{{rld|0x0d06002c|32|OHC1_HCBLKCUR||}}
 +
{{rld|0x0d060030|32|OHC1_HCDNHD||}}
 +
{{rld|0x0d060034|32|OHC1_HCFMINT||}}
 +
{{rld|0x0d060038|32|OHC1_HCFMREM||}}
 +
{{rld|0x0d06003c|32|OHC1_HCFMNUM||}}
 +
{{rld|0x0d060040|32|OHC1_HCPERST||}}
 +
{{rld|0x0d060044|32|OHC1_HCLSTHRESH||}}
 +
{{rld|0x0d060048|32|OHC1_HCRHDESCA||}}
 +
{{rld|0x0d06004c|32|OHC1_HCRHDESCB||}}
 +
{{rld|0x0d060050|32|OHC1_HCRHSTAT||}}
 +
{{rld|0x0d060054|32|OHC1_HCRHPORT1STAT||}}
 +
{{rld|0x0d060058|32|OHC1_HCRHPORT2STAT||}}
 +
|}

Latest revision as of 03:42, 29 March 2020

Enhanced Host Controller Interface (EHCI)

EHCI
Access
BroadwayNone
StarletFull
Registers
Base0x0d040000
Length0x100
Access size32 bits
Byte orderReversed Little Endian
IRQs
Hollywood4
This box: view • talk • edit


EHCI Registers
Address Bits Name Description
0x0d040000 32 EHC0_CAPLENVER
0x0d040004 32 EHC0_HCSPARAMS
0x0d040008 32 EHC0_HCCPARAMS
0x0d04000c 32 EHC0_HCSP_PORTROUTE
0x0d040010 32 EHC0_USBCMD
0x0d040014 32 EHC0_USBSTS
0x0d040018 32 EHC0_PRUSBINTR
0x0d040018 32 EHC0_USBINTR
0x0d04001c 32 EHC0_FRINDEX
0x0d040020 32 EHC0_CTRLDSSEGMENT
0x0d040024 32 EHC0_PERIODICLISTBASE
0x0d040028 32 EHC0_ASYNCICLISTADDR
0x0d040050 32 EHC0_PRCONFIGFLAG
0x0d040054 32 EHC0_PORTSC
0x0d040054 32 PORT_CTRL
0x0d040090 32 EHC_MISC_CTRL0
0x0d040094 32 EHC_PKTBUF_THRESHOLD
0x0d040098 32 USB_PHY_STS0
0x0d04009c 32 USB_PHY_STS1
0x0d0400a0 32 USB_PHY_STS2
0x0d0400a4 32 UTMI_CTRL
0x0d0400a8 32 BIST_CTRL
0x0d0400ac 32 EHC_MISC_CTRL1
0x0d0400b0 32 USB_PHYCMN_CAL
0x0d0400b4 32 PHYADJ_CTRL
0x0d0400c4 32 EHC_PKTBUF_DEPTH
0x0d0400c8 32 EHC_BREAK_MEM_XFR
0x0d0400cc 32 USB_CHICKENBITS


Open Host Controller Interface #0

OHCI0
Access
BroadwayNone
StarletFull
Registers
Base0x0d050000
Length0x200
Access size32[check] bits
Byte orderReversed Little Endian
IRQs
Hollywood5
This box: view • talk • edit


OHCI0 Registers
Address Bits Name Description
0x0d050000 32 OHC0_HCREV
0x0d050004 32 OHC0_HCCTRL
0x0d050008 32 OHC0_HCCMDSTAT
0x0d05000c 32 OHC0_HCINTSTAT
0x0d050010 32 OHC0_HCINTEN
0x0d050014 32 OHC0_HCINTDIS
0x0d050018 32 OHC0_HCHCCA
0x0d05001c 32 OHC0_HCPERCUR
0x0d050020 32 OHC0_HCCTRLHD
0x0d050024 32 OHC0_HCCTRLCUR
0x0d050028 32 OHC0_HCBLKHD
0x0d05002c 32 OHC0_HCBLKCUR
0x0d050030 32 OHC0_HCDNHD
0x0d050034 32 OHC0_HCFMINT
0x0d050038 32 OHC0_HCFMREM
0x0d05003c 32 OHC0_HCFMNUM
0x0d050040 32 OHC0_HCPERST
0x0d050044 32 OHC0_HCLSTHRESH
0x0d050048 32 OHC0_HCRHDESCA
0x0d05004c 32 OHC0_HCRHDESCB
0x0d050050 32 OHC0_HCRHSTAT
0x0d050054 32 OHC0_HCRHPORT1STAT
0x0d050058 32 OHC0_HCRHPORT2STAT


Open Host Controller Interface #1

OHCI1
Access
BroadwayNone
StarletFull
Registers
Base0x0d060000
Length0x200
Access size32[check] bits
Byte orderReversed Little Endian
IRQs
Hollywood6
This box: view • talk • edit


OHCI1 Registers
Address Bits Name Description
0x0d060000 32 OHC1_HCREV
0x0d060004 32 OHC1_HCCTRL
0x0d060008 32 OHC1_HCCMDSTAT
0x0d06000c 32 OHC1_HCINTSTAT
0x0d060010 32 OHC1_HCINTEN
0x0d060014 32 OHC1_HCINTDIS
0x0d060018 32 OHC1_HCHCCA
0x0d06001c 32 OHC1_HCPERCUR
0x0d060020 32 OHC1_HCCTRLHD
0x0d060024 32 OHC1_HCCTRLCUR
0x0d060028 32 OHC1_HCBLKHD
0x0d06002c 32 OHC1_HCBLKCUR
0x0d060030 32 OHC1_HCDNHD
0x0d060034 32 OHC1_HCFMINT
0x0d060038 32 OHC1_HCFMREM
0x0d06003c 32 OHC1_HCFMNUM
0x0d060040 32 OHC1_HCPERST
0x0d060044 32 OHC1_HCLSTHRESH
0x0d060048 32 OHC1_HCRHDESCA
0x0d06004c 32 OHC1_HCRHDESCB
0x0d060050 32 OHC1_HCRHSTAT
0x0d060054 32 OHC1_HCRHPORT1STAT
0x0d060058 32 OHC1_HCRHPORT2STAT
Retrieved from "https://wiibrew.org/w/index.php?title=Hardware/USB_Host_Controller&oldid=108383"