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Hollywood/Registers (view source)

Revision as of 15:02, 2 April 2020

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Line 8: Line 8:  
| hwdirq = 0,10,11,17,30,31,...{{check}}
 
| hwdirq = 0,10,11,17,30,31,...{{check}}
 
}}
 
}}
−
The Hollywood chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the powerPC. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starlet permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
+
The Hollywood chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the PowerPC. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starlet permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
    
See also the MINI source code, especially [http://gitweb.bootmii.org/?p=mini.git;a=blob;f=hollywood.h hollywood.h].
 
See also the MINI source code, especially [http://gitweb.bootmii.org/?p=mini.git;a=blob;f=hollywood.h hollywood.h].
Line 20: Line 20:  
{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
 
{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
 
{{rld|0x0d800014|32|HW_ALARM}}
 
{{rld|0x0d800014|32|HW_ALARM}}
−
{{rld|0x0d800018|32|HW_PPCSPEED|[[Hardware/PPC Speed Control|PPC Speed Control]]}}
+
{{rld|0x0d800018|32|HW_VI1CFG|VI-configuration related, unused?}}
−
{{rld|0x0d800030|32|HW_PPCIRQFLAG|[[Hardware/Hollywood IRQs|Hollywood IRQ controller]]|drs=4}}
+
{{rla|0x0d80001C|32|HW_VIDIM|Dims the video output}}
 +
{{rla|0x0d800024|32|HW_VISOLID|Sets the video output to a solid color}}
 +
{{rld|0x0d800030|32|HW_PPCIRQFLAG|[[Hardware/Hollywood IRQs|Hollywood IRQ controller]]|drs=12}}
 
{{rld|0x0d800034|32|HW_PPCIRQMASK}}
 
{{rld|0x0d800034|32|HW_PPCIRQMASK}}
 
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
 
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
 
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
 
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
−
{{rld|0x0d800060|32|HW_MEMIRR|Memory control / SRAM bank swap{{check}}}}
+
{{rld|0x0d800040|32|HW_ARMFIQMASK}}
−
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB}}
+
{{rld|0x0d800044|32|HW_IOPINTPPC}}
−
{{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
+
{{rld|0x0d800048|32|HW_WDGINTSTS}}
−
{{rld|0x0d800074|32|HW_DDRCTRL_ADDR|[[Hardware/DDR Control|DDR Control]]|drs=2}}
+
{{rld|0x0d80004c|32|HW_WDGCFG}}
−
{{rld|0x0d800076|32|HW_DDRCTRL_VAL}}
+
{{rld|0x0d800050|32|HW_DMAADRINTSTS}}
 +
{{rld|0x0d800054|32|HW_CPUADRINTSTS}}
 +
{{rld|0x0d800058|32|HW_DBGINTSTS}}
 +
{{rld|0x0d80005c|32|HW_DBGINTEN}}
 +
{{rla|0x0d800060|32|HW_SRNPROT|Probably bus control; includes the SRAM bank swap }}
 +
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}}
 +
{{rla|0x0d800070|32|HW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other; probably related to Flipper interface compatibility}}
 +
{{rla|0x0d800074|32|HW_AIPIOCTRL|Probably related to Flipper interface compatibility/bus control}}
 +
{{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}}
 +
{{rld|0x0d800084|32|HW_USBDBG1}}
 +
{{rld|0x0d800088|32|HW_USBFRCRST}}
 +
{{rld|0x0d80008c|32|HW_USBIOTEST}}
 +
{{rld|0x0d800090|32|HW_ELA_REG_ADDR|Unknown ("embedded logic-analyzer?!")|drs=4}}
 +
{{rld|0x0d800094|32|HW_ELA_REG_DATA}}
 +
{{rld|0x0d800098|32|HW_MEMTSTN}}
 +
{{rld|0x0d80009c|32|HW_MEMTSTP}}
 
{{rld|0x0d8000c0|32|HW_GPIOB_OUT|[[Hardware/Hollywood GPIOs|Hollywood GPIOs]]|drs=16}}
 
{{rld|0x0d8000c0|32|HW_GPIOB_OUT|[[Hardware/Hollywood GPIOs|Hollywood GPIOs]]|drs=16}}
 
{{rld|0x0d8000c4|32|HW_GPIOB_DIR}}
 
{{rld|0x0d8000c4|32|HW_GPIOB_DIR}}
Line 36: Line 53:  
{{rld|0x0d8000d0|32|HW_GPIOB_INTFLAG}}
 
{{rld|0x0d8000d0|32|HW_GPIOB_INTFLAG}}
 
{{rld|0x0d8000d4|32|HW_GPIOB_INTMASK}}
 
{{rld|0x0d8000d4|32|HW_GPIOB_INTMASK}}
−
{{rld|0x0d8000d8|32|HW_GPIOB_INMIR}}
+
{{rld|0x0d8000d8|32|HW_GPIOB_STRAPS}}
 
{{rld|0x0d8000dc|32|HW_GPIO_ENABLE}}
 
{{rld|0x0d8000dc|32|HW_GPIO_ENABLE}}
 
{{rld|0x0d8000e0|32|HW_GPIO_OUT}}
 
{{rld|0x0d8000e0|32|HW_GPIO_OUT}}
Line 44: Line 61:  
{{rld|0x0d8000f0|32|HW_GPIO_INTFLAG}}
 
{{rld|0x0d8000f0|32|HW_GPIO_INTFLAG}}
 
{{rld|0x0d8000f4|32|HW_GPIO_INTMASK}}
 
{{rld|0x0d8000f4|32|HW_GPIO_INTMASK}}
−
{{rld|0x0d8000f8|32|HW_GPIO_INMIR}}
+
{{rld|0x0d8000f8|32|HW_GPIO_STRAPS}}
 
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
 
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
−
{{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}}
+
{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers?|drs=18}}
−
{{rla|0x0d800184|32|HW_UNKFLAGS|{{check}}}}
+
{{rld|0x0d800104|32|HW_ARB_CFG_M1}}
−
{{rla|0x0d80018c|32|HW_BOOT0|Maps boot0 {{check}}}}
+
{{rld|0x0d800108|32|HW_ARB_CFG_M2}}
 +
{{rld|0x0d80010c|32|HW_ARB_CFG_M3}}
 +
{{rld|0x0d800110|32|HW_ARB_CFG_M4}}
 +
{{rld|0x0d800114|32|HW_ARB_CFG_M5}}
 +
{{rld|0x0d800118|32|HW_ARB_CFG_M6}}
 +
{{rld|0x0d80011c|32|HW_ARB_CFG_M7}}
 +
{{rld|0x0d800120|32|HW_ARB_CFG_M8}}
 +
{{rld|0x0d800124|32|HW_ARB_CFG_M9}}
 +
{{rld|0x0d800130|32|HW_ARB_CFG_MC}}
 +
{{rld|0x0d800134|32|HW_ARB_CFG_MD}}
 +
{{rld|0x0d800138|32|HW_ARB_CFG_ME}}
 +
{{rld|0x0d80013c|32|HW_ARB_CFG_MF}}
 +
{{rld|0x0d800140|32|HW_ARB_CFG_CPU}}
 +
{{rld|0x0d800144|32|HW_ARB_CFG_DMA}}
 +
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
 +
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
 +
{{rla|0x0d800180|32|HW_COMPAT| Some DI stuff and boot code and {{check}}}}
 +
{{rld|0x0d800184|32|HW_RESET_AHB|}}
 +
{{rld|0x0d800188|32|HW_SPARE0|?}}
 +
{{rla|0x0d80018c|32|HW_BOOT0|(ACR_SPARE1) Controls boot0 mapping? {{check}}}}
 
{{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}}
 
{{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}}
 
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
 
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
 
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
 
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
−
{{rla|0x0d8001b0|32|HW_ACRPLLSYS|?}}
+
{{rld|0x0d80019c|32|HW_PLLDR|PLL/Clock configuration (?)|drs=12}}
−
{{rla|0x0d8001b4|32|HW_ACRPLLSYSEXT|Clocking?}}
+
{{rla|0x0d8001b0|32|HW_PLLSYS}}
−
{{rld|0x0d8001dc|32|HW_SSPOWER|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}
+
{{rla|0x0d8001b4|32|HW_PLLSYSEXT}}
 +
{{rld|0x0d8001b8|32|HW_PLLDSK}}
 +
{{rld|0x0d8001bc|32|HW_PLLDDR}}
 +
{{rld|0x0d8001c0|32|HW_PLLDDREXT}}
 +
{{rld|0x0d8001c4|32|HW_PLLVI}}
 +
{{rla|0x0d8001c8|32|HW_PLLVIEXT}}
 +
{{rld|0x0d8001cc|32|HW_PLLAI}}
 +
{{rla|0x0d8001d0|32|HW_PLLAIEXT}}
 +
{{rld|0x0d8001d4|32|HW_PLLUSB}}
 +
{{rla|0x0d8001d8|32|HW_PLLUSBEXT}}
 +
{{rld|0x0d8001dc|32|HW_IOPWRCTRL|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}
 +
{{rld|0x0d8001e0|32|HW_IOSTRCTRL0|More clock registers?|drs=3}}
 +
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1}}
 +
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL}}
 
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001f0|32|HW_OTPDATA}}
 
{{rld|0x0d8001f0|32|HW_OTPDATA}}
−
{{rld|0x0d800214|32|HW_VERSION|Hollywood version}}
+
{{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers|drs=4}}
 +
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
 +
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
 +
{{rld|0x0d800200|32|HW_DBGPORT}}
 +
{{rld|0x0d800204|32|HW_SICLKDIV|SI-related, unused?|drs=4}}
 +
{{rld|0x0d800208|32|HW_SICTRL}}
 +
{{rld|0x0d80020c|32|HW_SIDATA}}
 +
{{rld|0x0d800210|32|HW_SIINT}}
 +
{{rla|0x0d800214|32|HW_VERSION|Hollywood version}}
 
{{rld|0x0d8b420a|16|MEM_PROT|MEM2 protection enable}}
 
{{rld|0x0d8b420a|16|MEM_PROT|MEM2 protection enable}}
 
{{rld|0x0d8b420c|16|MEM_PROT_START|MEM2 protection low address (upper 16 bits)}}
 
{{rld|0x0d8b420c|16|MEM_PROT_START|MEM2 protection low address (upper 16 bits)}}
Line 66: Line 123:     
== General Registers ==
 
== General Registers ==
−
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
+
{{reg32 | HW_VIDIM | addr=0x0d80001c | hifields = 1 | lofields = 5 |
 +
|16          |
 +
|?            |
 +
|            ||
 +
|8 |1  |1  |3  |3  |
 +
|? |R/W|R/W|R/W |R/W|
 +
|  |E  |  |Y  |C  ||
 +
}}
 +
This register controls dimming of the video output.
 +
{{regdesc
 +
|E|Turns Dimming on/off
 +
|Y|Amount to dim luma component (0-7)
 +
|C|Amount to dim chroma components (0-7)
 +
}}
 +
 
 +
{{reg32 | HW_VISOLID | addr = 0x0d800024 | hifields = 2 | lofields = 3 |
 +
|8      |8    |
 +
|R/W    |R/W  |
 +
|U      |V    ||
 +
|8      |7    |1|
 +
|R/W    |?    |R/W|
 +
|Y      |    |E  ||
 +
}}
 +
This register controls the solid color for VI.
 +
{{regdesc
 +
|U|U component
 +
|V|V component
 +
|Y|Luma component
 +
|E|Turns solid colour on/off
 +
}}
 +
 
 +
{{reg32 | HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 |
 +
|16          |
 +
|?            |
 +
|            ||
 +
|9 |1  |1  |1  |1  |1  |1  |1  |
 +
|? |R/W|R/W|R/W|R/W|R/W|R/W|R/W|
 +
|  |H  |SM |U4 |U3 |C  |B  |A  ||
 +
}}
 +
This register controls seems to control visibility of various devices or features.
 +
The value of the register during normal operation seems to depend on Hollywood revision.
 +
 
 +
* In boot1c, set to 0x47 if HWVER (in HW_VERSION) is 0 - otherwise, set to 0x7.
 +
* When BC is booting, set to 0x67 if HWVER is 0 - otherwise set to 0x27
 +
 
 +
 
 +
It seems like bits 31-7 cannot be read or written to? {{check}}
 +
{{regdesc
 +
|H|Set [by boot1, BC, others] if HWVER in HW_VERSION is 0
 +
|SM|Enables the SRAM mirror at 0xfffe0000 when set
 +
|U4|Unknown
 +
|U3|Set/cleared by syscall 0x54 in IOS58; maybe related to HW_AHBPROT
 +
|C|Explicitly set by boot0/boot1 before using NAND/AES/SHA
 +
|B|Explicitly set by boot0/boot1 before using NAND/AES/SHA
 +
|A|Explicitly set by boot0/boot1 before using NAND/AES/SHA
 +
}}
 +
 
 +
{{reg32 | HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 |
 
|16          |
 
|16          |
−
|U           |
+
|?           |
 
|            ||
 
|            ||
−
|8|4    |4    |
+
|11|1  |3|1        |
−
|U|R   |R   |
+
|? |R/W|?|R/W      |
−
| |VERHI|VERLO|
+
|  |DI | |ENAHBIOPI      ||
 
}}
 
}}
−
This register contains the hardware revision of the Hollywood chipset.
+
This register controls at least the current EXI status. It's probably related to bus control/GC compatibility.
 
{{regdesc
 
{{regdesc
−
|VERHI|Version
+
|DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}}
−
|VERLO|Revision
+
|ENAHBIOPI| "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI.
 
}}
 
}}
   −
{{reg32 | HW_EXICTRL | addr = 0x0d800070 | hifields = 1 | lofields = 2 |
+
{{reg32 | HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 |
 
|16          |
 
|16          |
 
|?            |
 
|?            |
 
|            ||
 
|            ||
 
|15|1        |
 
|15|1        |
−
|? |R/W      |
+
|? |?      |
−
|  |EXI      ||
+
|  |ENAHBIOMEM  ||
 
}}
 
}}
−
This register controls at least the current EXI status.
+
This register is probably related to bus control/GC compatibility.
 
{{regdesc
 
{{regdesc
−
|EXI|enable EXI bus
+
|ENAHBIOMEM| This bit is named in IOSv3.
 
}}
 
}}
   −
{{reg32 | HW_DIFLAGS | addr = 0x0d800180 | hifields = 3 | lofields = 1 |
+
 
−
|11        |1      |4             |
+
{{reg32 | HW_COMPAT| addr = 0x0d800180 | hifields = 4 | lofields = 5 |
−
|?         |R/W    |?             |
+
|10|1      |1      |4 |
−
|         |PPCBOOT|               ||
+
|? |R/W    |R/W    |? |
−
|16        |
+
| |DVDVIDEO|PPCBOOT| ||
−
|?         |
+
|11  |1 |2 |1  |1|
−
|         |
+
|?   |? |? |R/W |?|
 +
|   |B4|  |B1  | ||
 
}}
 
}}
−
This register seems to control some aspects of the powerpc booting and some di flags.{{check}}
+
This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}}
 
{{regdesc
 
{{regdesc
−
|PPCBOOT|needs to be set to allow the powerpc to read the boot stub.
+
|DVDVIDEO|Disables{{check}} DVD video support when set
−
|Bit 2 | when clear, disables bit 14 in the PPC IRQ flags
+
|PPCBOOT|needs to be set to allow the PowerPC to read the boot stub.
 +
|B4| Potentially related to the IOSTRCTRL registers?
 +
|B1| when clear, disables bit 14 in the PPC IRQ flags
 
}}
 
}}
   −
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 |
+
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 9 |
 
|16        |
 
|16        |
 
|? |
 
|? |
 
|          ||
 
|          ||
−
|1|2        |1     |12              |
+
|1|2        |1   |1  |1  |6    |1  |2 |1  |
−
|?|R/W|R/W     | ?    |
+
|?|R/W      |R/W  |R/W |R/W|?    |R/W|? |R/W|
−
|         |DSKPLLSRC|BOOT0|               |
+
| |DSKPLLSRC|BOOT0|B11 |B10|    |A3 |  |A0 ||
 
}}
 
}}
 
This register at least controls the boot0 memory mapping and DSK PLL source.
 
This register at least controls the boot0 memory mapping and DSK PLL source.
Line 119: Line 236:  
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
 
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
 
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
 
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
 +
|B11|Explicitly set by the [IOS58] kernel on boot
 +
|B10|Explicitly set by the [IOS58] kernel on boot
 +
|A3|AHB-related? - polled on AHB flush? Related to bit 16 in 0x0d800188?
 +
|A0|AHB-related? - polled on AHB flush? Related to bit 16 in 0x0d800188?
 
}}
 
}}
   Line 132: Line 253:  
{{regdesc
 
{{regdesc
 
|FX|Unknown, but IOS calls this "FX".
 
|FX|Unknown, but IOS calls this "FX".
−
|SPEED|Sets the Hollywood clock to 243MHz when 1 (Wii mode) or 162MHz when 0 (GC mode)  (or vice-versa?)
+
|SPEED|Sets the Hollywood clock to 243MHz when 0 (Wii mode) or 162MHz when 1 (GC mode)
 +
}}
 +
 
 +
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
 +
|5                      |1          |1        |1      |1      |1      |1      |1      |1        |1        |1        |1        |
 +
|U                      |R/W        |R/W      |R/W    |R/W    |R/W    |R/W    |R/W    |R/W      |R/W      |R/W      |R/W      |
 +
|                        |NLCKB_EDRAM|RSTB_EDRAM|RSTB_AHB|RSTB_IOP|RSTB_DSP|RSTB_VI1|RSTB_VI|RSTB_IOPI|RSTB_IOMEM|RSTB_IODI|RSTB_IOEXI||
 +
|1        |1          |1      |1          |1      |1          |1      |1          |1          |1          |1        |1      |1          |1          |1    |1      |
 +
|R/W      |R/W        |R/W    |R/W        |R/W    |R/W        |R/W    |R/W        |R/W        |R/W        |R/W      |R/W    |R/W        |R/W        |R/W |R/W    |
 +
|RSTB_IOSI|RSTB_AI_I2S3|RSTB_GFX|RSTB_GFXTCPE|RSTB_MEM|RSTB_DIRSTB|RSTB_PI|RSTB_MEMRSTB|NLCKB_SYSPLL|RSTB_SYSPLL|SRSTB_CPU|RSTB_CPU|RSTB_DSKPLL|RSTB_MEMRSTB|CRSTB|RSTBINB|
 +
}}
 +
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
 +
{{regdesc
 +
|NLCKB_EDRAM| Unlock external DRAM reset?
 +
|RSTB_EDRAM| External DRAM reset
 +
|RSTB_AHB| ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...
 +
|RSTB_IOP| IOP/Starlet reset
 +
|RSTB_VI1| VI1 reset?
 +
|RSTB_VI| Video Interface reset
 +
|RSTB_IOPI| [[Hardware/Processor_Interface|Processor Interface IO]] reset
 +
|RSTB_IOMEM| [[Hardware/Memory_Interface|MEM IO]] reset
 +
|RSTB_IODI| Disk Interface IO reset
 +
|RSTB_IOEXI| EXI IO reset
 +
|RSTB_IOSI| SI IO reset
 +
|RSTB_AI_I2S3| Audio interface I2S3 reset
 +
|RSTB_GFX| GFX reset?
 +
|RSTB_GFXTCPE| GFX TCPE?
 +
|RSTB_MEM| [[Hardware/Memory_Interface|MEM]] reset. If cleared, kills EXI-based starlet experimental proxy.
 +
|RSTB_DIRSTB| Disk Interface reset B
 
}}
 
}}
   −
{{reg32 | HW_ACRPLLSYS | addr = 0x0d8001b0 | hifields = 2 | lofields = 1 |
+
 
−
|9       |7     |
+
{{regdesc
−
|R/W?| ? |
+
|NLCKB_SYSPLL| Unlock SYSPLL reset?
−
|clk_0|||
+
|RSTB_SYSPLL| SYSPLL reset. If cleared, kills EXI-based starlet experimental proxy.
 +
|SRSTB_CPU| PowerPC SRESET (release first)
 +
|RSTB_CPU| PowerPC HRESET (release second)
 +
|RSTB_DSKPLL| DSKPLL reset. Is cleared by IOS before modifying 1b8, and set again afterwards
 +
|RSTB_MEMRSTB| MEM reset B. Also seems to reboot system.
 +
|CRSTB| CRST? Also seems to reboot system.
 +
|RSTBINB| System reset. Set to zero to reboot system.
 +
}}
 +
 
 +
{{reg32 | HW_PLLSYS | addr = 0x0d8001b0 | hifields = 3 | lofields = 1 |
 +
|5       |9     |2|
 +
|?|R/W?| ? |
 +
||clk_0|||
 
|16      |
 
|16      |
 
|?      |
 
|?      |
Line 148: Line 309:  
}}
 
}}
   −
{{reg32 | HW_ACRPLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
+
{{reg32 | HW_PLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
 
|16      |
 
|16      |
 
|?      |
 
|?      |
Line 154: Line 315:  
|7        |9      |
 
|7        |9      |
 
||R/W?|
 
||R/W?|
−
||clk_1||
+
||CPUCLK||
 
}}
 
}}
 
This register is involved in some sort of clocking.
 
This register is involved in some sort of clocking.
 
{{regdesc
 
{{regdesc
−
|clk_1|Unknown, but IOS calls this "clk_1".
+
|CPUCLK|IOS calls this "clk_1". 100J calls this "CPUCLK". This is probably the bus speed. Bit 8 is never set? <br>
 +
 
 +
243Mhz - 0x10<br>
 +
216Mhz - 0x12<br>
 +
194Mhz - 0x14<br>
 +
176Mhz - 0x16<br>
 +
162Mhz - 0x18<br>
 +
149Mhz - 0x1a<br>
 +
138Mhz - 0x1c<br>
 +
129Mhz - 0x1e<br>
 +
121Mhz - 0x20<br>
 +
114Mhz - 0x22<br>
 +
108Mhz - 0x24
 
}}
 
}}
   −
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
+
{{reg32 | HW_PLLVIEXT | addr = 0x0d8001c8 | hifields = 3 | lofields = 1 |
−
|5                      |1  |1   |1  |1  |1  |1  |1  |1  |1  |1  |1  |
+
|1    |1  | 14|
−
|U                      |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
+
|R/W? |R/W?|  ? |
−
|                        |A   |B  |HANG|D  |E  |F  |G  |DDR2|I  |DI2 |DDR1||
+
|A    |B   |   ||
−
|1  |1  |1   |1  |1   |1  |1  |1  |1  |1  |1  |1  |1  |1   |1  |1  |
+
|16            |
−
|R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
+
|?              |
−
|L  |M  |N  |O  |P  |DI  |R  |S  |T  |U   |PPC1|PPC2|V  |SYS3|SYS2|SYS |
+
|             ||
 +
}}
 +
Probably related to VI clocking.
 +
{{regdesc
 +
|A|Related to VI PLL initialization?
 +
|B|Related to VI PLL initialization?
 +
}}
 +
 
 +
 
 +
 
 +
{{reg32 | HW_PLLAIEXT | addr = 0x0d8001d0 | hifields = 3 | lofields = 1 |
 +
|1    |1  | 14|
 +
|R/W? |R/W?| ? |
 +
|A   |B  |   ||
 +
|16            |
 +
|?              |
 +
|             ||
 +
}}
 +
Probably related to AI clocking.
 +
{{regdesc
 +
|A|Related to AI PLL initialization?
 +
|B|Related to AI PLL initialization?
 +
}}
 +
 
 +
 
 +
{{reg32 | HW_PLLUSBEXT | addr = 0x0d8001d8 | hifields = 3 | lofields = 1 |
 +
|1   |1  | 14|
 +
|R/W? |R/W?| ? |
 +
|A    |B   |   ||
 +
|16            |
 +
|?              |
 +
|             ||
 +
}}
 +
Probably related to USB clocking.
 +
{{regdesc
 +
|A|Related to USB PLL initialization?
 +
|B|Related to USB PLL initialization?
 +
}}
 +
 
 +
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
 +
|16          |
 +
|U            |
 +
|             ||
 +
|8|4    |4    |
 +
|U|R    |R    |
 +
| |HWVER|HWREV|
 
}}
 
}}
−
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
+
This register contains the hardware revision of the Hollywood chipset. Observed values:
 +
 
 +
* Hollywood ES1.x - 0x00 to 0x0f (?)<br>
 +
* Hollywood ES2.0 - 0x10<br>
 +
* Hollywood ES2.1 - 0x11
 +
 
 
{{regdesc
 
{{regdesc
−
|HANG|System reset without recovery? Kills DI, sets slot LED on, hangs starlet...
+
|HWVER|Hollywood Version
−
|DDR2|seems to be related to the GDDR3 memory
+
|HWREV|Hollywood Revision
−
|DI2|DI reset 2?
  −
|DDR1|seems to be related to the GDDR3 memory
  −
|P|If cleared, kills EXI-based starlet experimental proxy.
  −
|DI|DI reset
  −
|U|If cleared, kills EXI-based starlet experimental proxy.
  −
|V|Is cleared by IOS before modifying 1b8, and set again afterwards
  −
|PPC1|PowerPC Reset 1 (release first)
  −
|PPC2|PowerPC Reset 2 (release second)
  −
|SYS3|System reset 3. Also seems to reboot system.
  −
|SYS2|System reset 2. Also seems to reboot system.
  −
|SYS|System reset. Set to zero to reboot system.
   
}}
 
}}
 +
 +
 
{{hwstub}}
 
{{hwstub}}
Retrieved from "https://wiibrew.org/wiki/Special:MobileDiff/99163...108397"

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