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{{Infobox MMIO
| ppc = Full
| arm = Full
| base = 0x0c004000
| len = 0x80
| bits = 16/32
| ppcirq = 7
}}
{{hwstub}}
{{yagcd}}
Protected memory is always 1 page long (page size is 1024 bytes), and you can specify only 4 protected regions. If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Because there are only 4 protected regions, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.
== Registers ==
{{reg32 | MI_PROT_RGN0 | addr = 0x0C004000 | hifields = 1 | lofields = 1 |
|16 |
|R/W |
|Low 16 bits of protected address ||
|16 |
|R/W |
|High 16 bits of protected address |
|}}
{{reg32 | MI_PROT_RGN1 | addr = 0x0C004004 | hifields = 1 | lofields = 1 |
|16 |
|R/W |
|Low 16 bits of protected address ||
|16 |
|R/W |
|High 16 bits of protected address |
|}}
{{reg32 | MI_PROT_RGN2 | addr = 0x0C004008 | hifields = 1 | lofields = 1 |
|16 |
|R/W |
|Low 16 bits of protected address ||
|16 |
|R/W |
|High 16 bits of protected address |
|}}
{{reg32 | MI_PROT_RGN3 | addr = 0x0C00400C | hifields = 1 | lofields = 1 |
|16 |
|R/W |
|Low 16 bits of protected address ||
|16 |
|R/W |
|High 16 bits of protected address |
|}}
This is most likely the same as (or at least ''mostly'' similar to) the Memory Interface on the Flipper chip (see [[YAGCD|YAGCD]]).<br>These registers are used by some programs (running on Broadway) to perform indirect accesses on the [[Hardware/Memory Controller|Memory Controller]] registers. The Memory Interface is also exposed to Hollywood starting at 0x0d8b4000. <br>{{reglist|Memory Interface Registers}}{{rld|0x0d8b4000|16|MEM_MARR0_START|[[Hardware/Memory Interface#Memory Protection|Memory Protection]]|drs=8}}{{rld|0x0d8b4002|16|MEM_MARR0_END}}{{rld|0x0d8b4004|16|MEM_MARR1_START}}{{rld|0x0d8b4006|16|MEM_MARR1_END}}{{rld|0x0d8b4008|16|MEM_MARR2_START}}{{rld|0x0d8b400a|16|MEM_MARR2_END}}{{rld|0x0d8b400c|16|MEM_MARR3_START}}{{rld|0x0d8b400e|16|MEM_MARR3_END}}{{rld|0x0d8b4010|16|MEM_MARR_CONTROL |MARR{0-3} permissions|}}{{rld|0x0d8b4012|16|MEM_CP_BW_DIAL |Bandwidth Dial (Command Processor)|}}{{rld|0x0d8b4014|16|MEM_TC_BW_DIAL |Bandwidth Dial (Texture Control)|}}{{rld|0x0d8b4016|16|MEM_PE_BW_DIAL |Bandwidth Dial (Pixel Engine)|}}{{rld|0x0d8b4018|16|MEM_CPUR_BW_DIAL |Bandwidth Dial (CPU read)|}}{{rld|0x0d8b401a|16|MEM_CPUW_BW_DIAL |Bandwidth Dial (CPU write)|}}{{rld|0x0d8b401c|16|MEM_INT_ENBL |MARR interrupt enable|}}{{rld|0x0d8b401e|16|MEM_INT_STAT |MARR interrupt status|}}{{rld|0x0d8b4020|16|MEM_INT_CLR |MARR interrupt clear/mask (?)|}}{{rld|0x0d8b4022|16|MEM_INT_ADDRL |MARR interrupt address (lo bits)|}}{{rld|0x0d8b4024|16|MEM_INT_ADDRH |MARR interrupt address (hi bits)|}}{{rld|0x0d8b4026|16|MEM_REFRESH ||}}{{rld|0x0d8b4028|16|MEM_CONFIG ||}}{{rld|0x0d8b402a|16|MEM_LATENCY ||}}{{rld|0x0d8b402c|16|MEM_RDTORD ||}}{{rld|0x0d8b402e|16|MEM_RDTOWR ||}}{{rld|0x0d8b4030|16|MEM_WRTORD ||}}{{rld|0x0d8b4032|16|MEM_CP_REQCOUNTH |Memory Request Count (Command Processor) (hi bits)|}}{{rld|0x0d8b4034|16|MEM_CP_REQCOUNTL |Memory Request Count (Command Processor) (lo bits)|}}{{rld|0x0d8b4036|16|MEM_TC_REQCOUNTH |Memory Request Count (Texture Control) (hi bits)|}}{{rld|0x0d8b4038|16|MEM_TC_REQCOUNTL |Memory Request Count (Texture Control) (lo bits)|}}{{rld|0x0d8b403a|16|MEM_CPUR_REQCOUNTH |Memory Request Count (CPU read) (hi bits)|}}{{rld|0x0d8b403c|16|MEM_CPUR_REQCOUNTL |Memory Request Count (CPU read) (lo bits)|}}{{rld|0x0d8b403e|16|MEM_CPUW_REQCOUNTH |Memory Request Count (CPU write) (hi bits)|}}{{rld|0x0d8b4040|16|MEM_CPUW_REQCOUNTL |Memory Request Count (CPU write) (lo bits)|}}{{rld|0x0d8b4042|16|MEM_DSP_REQCOUNTH |Memory Request Count (DSP) (hi bits)|}}{{rld|0x0d8b4044|16|MEM_DSP_REQCOUNTL |Memory Request Count (DSP) (lo bits)|}}{{rld|0x0d8b4046|16|MEM_IO_REQCOUNTH |Memory Request Count (I/O) (hi bits)|}}{{rld|0x0d8b4048|16|MEM_IO_REQCOUNTL |Memory Request Count (I/O) (lo bits)|}}{{rld|0x0d8b404a|16|MEM_VI_REQCOUNTH |Memory Request Count (Video Interface) (hi bits)|}}{{rld|0x0d8b404c|16|MEM_VI_REQCOUNTL |Memory Request Count (Video Interface) (lo bits)|}}{{rld|0x0d8b404e|16|MEM_PE_REQCOUNTH |Memory Request Count (Pixel Engine) (hi bits)|}}{{rld|0x0d8b4050|16|MEM_PE_REQCOUNTL |Memory Request Count (Pixel Engine) (lo bits)|}}{{rld|0x0d8b4052|16|MEM_RF_REQCOUNTH ||}}{{rld|0x0d8b4054|16|MEM_RF_REQCOUNTL ||}}{{rld|0x0d8b4056|16|MEM_FI_REQCOUNTH ||}}{{rld|0x0d8b4058|16|MEM_FI_REQCOUNTL ||}}{{rld|0x0d8b405a|16|MEM_DRV_STRENGTH ||}}{{rld|0x0d8b405c|16|MEM_REFRSH_THHD ||}}{{rld|0x0d8b4060|16|MEM_CPUAHMR_REQCOUNTH ||}}{{rld|0x0d8b4062|16|MEM_CPUAHMR_REQCOUNTL ||}}{{rld|0x0d8b4064|16|MEM_CPUAHMW_REQCOUNTH ||}}{{rld|0x0d8b4066|16|MEM_CPUAHMW_REQCOUNTL ||}}{{rld|0x0d8b4068|16|MEM_DMAAHMR_REQCOUNTH ||}}{{rld|0x0d8b406a|16|MEM_DMAAHMR_REQCOUNTL ||}}{{rld|0x0d8b406c|16|MEM_DMAAHMW_REQCOUNTH ||}}{{rld|0x0d8b406e|16|MEM_DMAAHMW_REQCOUNTL ||}}{{rld|0x0d8b4070|16|MEM_ACC_REQCOUNTH ||}}{{rld|0x0d8b4072|16|MEM_ACC_REQCOUNTL ||}}{{rld|0x0d8b4074|16|MEM_DDRREG_ADDR |DDR register offset|}}{{rld|0x0d8b4076|16|MEM_DDRREG_DATA |DDR register data|}}{{rld|0x0d8b4078|16|MEM_DRV_PSTRENGTH ||}}|}    = Memory Protection =The MARR registers are used to configure memory protection (where the granularity of particular regions are defined as a chunk of pages).Protected memory is always 1 page long (where page size is 1024 bytes). If the CPU tries to access the protected region in a way that is not allowed, an external interrupt will be raised. Page addresses are calculated with (physical_address >> 10). {{check}} {{regsimple | MEM_MARR0_START | addr = 0x0C004000 | bits = 16 | access = R/W}}{{regsimple | MEM_MARR0_END | addr = 0x0C004002 | bits = 16 | access = R/W}}{{regsimple | MEM_MARR1_START | addr = 0x0C004004 | bits = 16 | access = R/W}}{{regsimple | MEM_MARR1_END | addr = 0x0C004006 | bits = 16 | access = R/W}}{{regsimple | MEM_MARR2_START | addr = 0x0C004008 | bits = 16 | access = R/W}}{{regsimple | MEM_MARR2_END | addr = 0x0C00400a | bits = 16 | access = R/W}}{{regsimple | MEM_MARR3_START | addr = 0x0C00400c | bits = 16 | access = R/W}}{{regsimple | MEM_MARR3_END | addr = 0x0C00400e | bits = 16 | access = R/W}}  {{reg16 | MI_PROT_TYPE MEM_MARR_CONTROL | addr = 0x0C004010 | fields = 5 |
|8 |2 |2 |2 |2 |
|U |R/W |R/W |R/W |R/W |
}}
{{reg16 | MI_INTMASK MEM_INT_ENBL | addr = 0x0C00401C | fields = 6 |
|11 |1 |1 |1 |1 |1 |
|U |?/W |?/W |?/W |?/W |?/W |
|ChAll|When set, all MI interrupts are enabled.
}}
 {{reg16 | MI_INTFLAG MEM_INT_STAT | addr = 0x0C00401E | fields = 6 |
|11 |1 |1 |1 |1 |1 |
|U |R/W |R/W |R/W |R/W |R/W |
|ChAll|All MI interrupts. (?)
}}
{{reg16 | MI_UNKNOWN1 MEM_INT_CLR | addr = 0x0C004020 | fields = 3 |
|14 |1 |1 |
|U |? |U |
}}
{{reg16 | MI_PROT_ADDRLO MEM_INT_ADDRL | addr = 0x0C004022 | fields = 2 |
|11 |5 |
|R/? |U |
|Low | |
|}}
{{reg16 | MI_PROT_ADDRHI MEM_INT_ADDRH | addr = 0x0C004024 | fields = 2 |
|2 |14 |
|U |R/? |

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