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}}
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 3 4 |
|16 |
|? |
| ||
|3 1|2 |1 |12 ||?|R/W|R/W | ? || |DSKPLLSRC|BOOT0| |
}}
This register at least control controls the boot0 memory mappingand DSK PLL source.
{{regdesc
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
}}
This register is involved in some sort of clocking.
{{regdesc
|FXclk_0|Unknown, but IOS calls this "clk_0".
}}
This register is involved in some sort of clocking.
{{regdesc
|FXclk_1|Unknown, but IOS calls this "clk_1".
}}
|DI|DI reset
|U|If cleared, kills EXI-based starlet experimental proxy.
|V|Is cleared by IOS before modifying 1b8, and set again afterwards
|PPC1|PowerPC Reset 1 (release first)
|PPC2|PowerPC Reset 2 (release second)

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