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{{yagcd}}
== GX FIFO ==
Graphics processor commands can be 8bit or 32bit, but they must be sent padded to 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.
The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.

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