Hardware/DSP: Difference between revisions

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m Less known registers.
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m More stuff.
Line 71: Line 71:
{{reg16 | DSP_AR_SIZE | addr = 0xCC005012 | fields = 1 |
{{reg16 | DSP_AR_SIZE | addr = 0xCC005012 | fields = 1 |
|16  |
|16  |
|?   |
|R/? |
|Size|
|Size|
|}}
|}}
Line 80: Line 80:
{{reg16 | DSP_AR_MODE | addr = 0xCC005016 | fields = 1 |
{{reg16 | DSP_AR_MODE | addr = 0xCC005016 | fields = 1 |
|16  |
|16  |
|?   |
|?/W |
|Mode|
|Mode|
|}}
|}}
Line 120: Line 120:
|DSTADDR|The High half-word of the DMA Destination in ARAM.
|DSTADDR|The High half-word of the DMA Destination in ARAM.
}}
}}
{{reg16 | DSP_AR_DMA_SRC_L | addr = 0xCC005026 | fields = 1 |
{{reg16 | DSP_AR_DMA_DST_L | addr = 0xCC005026 | fields = 1 |
|16    |
|16    |
|?/W    |
|?/W    |
Line 127: Line 127:
{{regdesc
{{regdesc
|DSTADDR|The Low half-word of the DMA Destination in ARAM.
|DSTADDR|The Low half-word of the DMA Destination in ARAM.
}}
{{reg16 | DSP_AR_DMA_SIZE_H | addr = 0xCC005028 | fields = 2 |
|1  |15    |
|?/W |?/W    |
|Type|Size  |
|}}
{{regdesc
|Type|The type of DMA transfer. If 0, Write to ARAM. If 1, Read from ARAM.
|Size|The High half-word of the size of the DMA.
}}
{{reg16 | DSP_AR_DMA_SIZE_L | addr = 0xCC00502A | fields = 1 |
|16    |
|?/W    |
|Size  |
|}}
{{regdesc
|Size|The Low half-word of the size of the DMA.
}}
{{reg16 | DSP_DMA_START_ADDR_H | addr = 0xCC005030 | fields = 1 |
|16    |
|?/W    |
|ADDR  |
|}}
{{regdesc
|ADDR|Not exactly sure what this is for. Top halfword of the address.
}}
{{reg16 | DSP_DMA_START_ADDR_L | addr = 0xCC005032 | fields = 1 |
|16    |
|?/W    |
|ADDR  |
|}}
{{regdesc
|ADDR|Not exactly sure what this is for. Bottom halfword of the address.
}}
{{reg16 | DSP_DMA_CONTROL_LENGTH | addr = 0xCC005036 | fields = 2 |
|1    |15    |
|?/W  |?/W    |
|CTRL |LENGTH |
|}}
{{regdesc
|CTRL|If set, start playing the sample. If cleared, stop playing.
|LENGTH|Length of the sample divided by 32. The maximum value for this is 0x000FFFE0.
}}
{{reg16 | DSP_DMA_BYTES_LEFT | addr = 0xCC00503A | fields = 1 |
|16    |
|R/?  |
|BYTES |
|}}
{{regdesc
|BYTES|Count down to 0, counting how many bytes are left.
}}
}}

Revision as of 00:02, 20 July 2009

DSP
Access
BroadwayFull
StarletNone
Registers
Base0x0c005000
Length0x200
Access size16/32 bits
Byte orderBig Endian
IRQs
Broadway6
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Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue.

As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000)

Registers

DSP_MAILBOX_IN_H (0xCC005000)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field Set Data
Field Description
Set This must be set for the DSP to accept the data.
Data This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP.

DSP_MAILBOX_IN_L (0xCC005002)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP.


DSP_MAILBOX_OUT_H (0xCC005004)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R
Field Set Data
Field Description
Set This must be set for the data to be valid.
Data This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP.

DSP_MAILBOX_OUT_L (0xCC005006)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R
Field Data
Field Description
Data This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP.


DSP_CONTROL_STATUS (0xCC00500A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U W W W W R/W W R/W W R/W R/W R/W R/W
Field Reset ? DMAINT DMAINTMSK DSPINT ARINTMSK ARINT AIDINTMSK AIDINT HALT PIINT RES
Field Description
Reset Resets the DSP?
DMAINT DSP DMA Interrupt Status
DMAINTMSK DSP Interrupt Mask
DSPINT DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
ARINTMSK ARAM Interrupt Mask
ARINT ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
AIDINTMSK AI Interrupt Mask
AIDINT AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt.
HALT Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume.
PIINT DSP Interrupt Assertion? Setting asserts the DSP Interrupt.
RES Writing 1 resets the DSP.


DSP_AR_SIZE (0xCC005012)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/?
Field Size
Field Description
Size I can only guess that it's the size of the ARAM.


DSP_AR_MODE (0xCC005016)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field Mode
Field Description
Mode Some ARAM mode setting. Needs investigation.


DSP_AR_REFRESH (0xCC00501A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field Refresh
Field Description
Refresh Refreshes the ARAM?


DSP_AR_DMA_SRC_H (0xCC005020)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field SRCADDR
Field Description
SRCADDR The High half-word of the DMA Source.

DSP_AR_DMA_SRC_L (0xCC005022)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field SRCADDR
Field Description
SRCADDR The Low half-word of the DMA Source.

DSP_AR_DMA_DST_H (0xCC005024)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field DSTADDR
Field Description
DSTADDR The High half-word of the DMA Destination in ARAM.

DSP_AR_DMA_DST_L (0xCC005026)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field DSTADDR
Field Description
DSTADDR The Low half-word of the DMA Destination in ARAM.


DSP_AR_DMA_SIZE_H (0xCC005028)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W ?/W
Field Type Size
Field Description
Type The type of DMA transfer. If 0, Write to ARAM. If 1, Read from ARAM.
Size The High half-word of the size of the DMA.

DSP_AR_DMA_SIZE_L (0xCC00502A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field Size
Field Description
Size The Low half-word of the size of the DMA.


DSP_DMA_START_ADDR_H (0xCC005030)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field ADDR
Field Description
ADDR Not exactly sure what this is for. Top halfword of the address.

DSP_DMA_START_ADDR_L (0xCC005032)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W
Field ADDR
Field Description
ADDR Not exactly sure what this is for. Bottom halfword of the address.


DSP_DMA_CONTROL_LENGTH (0xCC005036)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?/W ?/W
Field CTRL LENGTH
Field Description
CTRL If set, start playing the sample. If cleared, stop playing.
LENGTH Length of the sample divided by 32. The maximum value for this is 0x000FFFE0.

DSP_DMA_BYTES_LEFT (0xCC00503A)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/?
Field BYTES
Field Description
BYTES Count down to 0, counting how many bytes are left.
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