Hardware/DSP: Difference between revisions
< Hardware
New page: {{Infobox MMIO | ppc = Full | base = 0x0c005000 | len = 0x200 | bits = 16/32 | ppcirq = 6 }} {{hwstub}} {{yagcd}} |
Initial stuff. Further adds to this page will be Minor Edits, to prevent spamming the Recent Changes. |
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{{hwstub}} | {{hwstub}} | ||
{{yagcd}} | {{yagcd}} | ||
Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue. | |||
As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000) | |||
== Registers == | |||
{{reg16 | DSP_MAILBOX_IN_H | addr = 0xCC005000 | fields = 2 | | |||
|1 |15 | | |||
|R/W |R/W | | |||
|Set |Data| | |||
|}} | |||
{{regdesc | |||
|Set |This must be set for the DSP to accept the data. | |||
|Data|This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP. | |||
}} | |||
{{reg16 | DSP_MAILBOX_IN_L | addr = 0xCC005002 | fields = 1 | | |||
|16 | | |||
|R/W | | |||
|Data| | |||
|}} | |||
{{regdesc | |||
|Data|This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP. | |||
}} | |||
{{reg16 | DSP_MAILBOX_OUT_H | addr = 0xCC005004 | fields = 2 | | |||
|1 |15 | | |||
|R |R | | |||
|Set |Data| | |||
|}} | |||
{{regdesc | |||
|Set |This must be set for the data to be valid. | |||
|Data|This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP. | |||
}} | |||
{{reg16 | DSP_MAILBOX_OUT_L | addr = 0xCC005006 | fields = 1 | | |||
|16 | | |||
|R | | |||
|Data| | |||
|}} | |||
{{regdesc | |||
|Data|This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP. | |||
}} | |||
{{reg16 | DSP_CONTROL_STATUS | addr = 0xCC00500A | fields = 13 | | |||
|4 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 | | |||
|U |W |W |W |W |R/W |W |R/W |W |R/W |R/W |R/W |R/W | | |||
| |Reset|? |DMAINT |DMAINTMSK |DSPINT |ARINTMSK |ARINT |AIDINTMSK |AIDINT |HALT |PIINT |RES | | |||
|}} | |||
{{regdesc | |||
|Reset|Resets the DSP? | |||
|DMAINT|DSP DMA Interrupt Status | |||
|DMAINTMSK|DSP Interrupt Mask | |||
|DSPINT|DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. | |||
|ARINTMSK|ARAM Interrupt Mask | |||
|ARINT|ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. | |||
|AIDINTMSK|AI Interrupt Mask | |||
|AIDINT|AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. | |||
|HALT|Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume. | |||
|PIINT|DSP Interrupt Assertion? Setting asserts the DSP Interrupt. | |||
|RES|Writing 1 resets the DSP. | |||
}} | |||
Revision as of 22:15, 19 July 2009
| DSP | |
| Access | |
|---|---|
| Broadway | Full |
| Starlet | None |
| Registers | |
| Base | 0x0c005000 |
| Length | 0x200 |
| Access size | 16/32 bits |
| Byte order | Big Endian |
| IRQs | |
| Broadway | 6 |
| This Hardware-related article is a stub. You can help WiiBrew by expanding it. |
| This article may be improved with information from Yet Another GameCube Documentation. You can help WiiBrew by expanding this article with the information and wikifying it. |
Excuse the crudity of these notes, they're written at 5:00 without any caffeine, and mostly copied from YAGCD with some nice formatting glue.
As the Infobox states, the base of this is at physical address 0x0C005000 (software address 0xCC005000)
Registers
| DSP_MAILBOX_IN_H (0xCC005000) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | R/W | ||||||||||||||
| Field | Set | Data | ||||||||||||||
| Field | Description |
| Set | This must be set for the DSP to accept the data. |
| Data | This, combined with the Data in DSP_MAILBOX_IN_L is the data being sent to the DSP. |
| DSP_MAILBOX_IN_L (0xCC005002) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R/W | |||||||||||||||
| Field | Data | |||||||||||||||
| Field | Description |
| Data | This, combined with the Data in DSP_MAILBOX_IN_H is the data being sent to the DSP. |
| DSP_MAILBOX_OUT_H (0xCC005004) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R | R | ||||||||||||||
| Field | Set | Data | ||||||||||||||
| Field | Description |
| Set | This must be set for the data to be valid. |
| Data | This, combined with the Data in DSP_MAILBOX_OUT_L is the data being sent from the DSP. |
| DSP_MAILBOX_OUT_L (0xCC005006) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | R | |||||||||||||||
| Field | Data | |||||||||||||||
| Field | Description |
| Data | This, combined with the Data in DSP_MAILBOX_OUT_H is the data being sent from the DSP. |
| DSP_CONTROL_STATUS (0xCC00500A) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | W | W | W | W | R/W | W | R/W | W | R/W | R/W | R/W | R/W | |||
| Field | Reset | ? | DMAINT | DMAINTMSK | DSPINT | ARINTMSK | ARINT | AIDINTMSK | AIDINT | HALT | PIINT | RES | ||||
| Field | Description |
| Reset | Resets the DSP? |
| DMAINT | DSP DMA Interrupt Status |
| DMAINTMSK | DSP Interrupt Mask |
| DSPINT | DSP Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. |
| ARINTMSK | ARAM Interrupt Mask |
| ARINT | ARAM Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. |
| AIDINTMSK | AI Interrupt Mask |
| AIDINT | AI Interrupt Status. When read, set means Interrupt is active. Clear is no interrupts. Writing 0 does nothing, while writing 1 clears interrupt. |
| HALT | Halt DSP? When set, the DSP will halt. When cleared, the DSP will resume. |
| PIINT | DSP Interrupt Assertion? Setting asserts the DSP Interrupt. |
| RES | Writing 1 resets the DSP. |