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Hardware/GX/Blitting Processor (view source)
Revision as of 09:16, 8 October 2011
, 09:16, 8 October 2011→Vertical filter registers
The Blitting Processor is a component of the Wii's GX subsystem. It is responsible for copying the EFB to the XFB, doing the RGBA->YCbCr conversion and scaling/antialiasing in the process.
The Blitting Processor is a component of the Wii's GX subsystem. It is responsible for copying the EFB to the XFB, doing the RGBA->YCbCr conversion and scaling/antialiasing in the process.
==BP (blitting processor) registers==
== BP (blitting processor) registers ==
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
===EFB source registers===
=== EFB source registers ===
One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:
One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:
{{reg24 | GX_BP_EFB_BOXCOORD | addr = 0x49 | fields = 3 |
{{reg24 | GX_BP_EFB_BOXCOORD | addr = 0x49 | fields = 3 |
* 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)
* 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)
===XFB destination registers===
=== XFB destination registers ===
The destination of the copy in the XFB is specified by the '''physical''' address of the XFB and the row stride (basically width of row, but no scaling appled).
The destination of the copy in the XFB is specified by the '''physical''' address of the XFB and the row stride (basically width of row, but no scaling appled).
{{regsimple | GX_BP_XFB_ADDR | addr=0x4B | bits=24 | access = R/W}}
{{regsimple | GX_BP_XFB_ADDR | addr=0x4B | bits=24 | access = R/W}}
* 0x4d: Low 10 bits specify row stride of destination.
* 0x4d: Low 10 bits specify row stride of destination.
===Copy control register===
=== Copy control register ===
{{reg24 | GX_BP_COPY_CONTROL | addr = 0x52 | fields = 4 |
{{reg24 | GX_BP_COPY_CONTROL | addr = 0x52 | fields = 4 |
|10|2 |1 | 11|
|10|2 |1 | 11|
===Copy clear registers===
=== Copy clear registers ===
Where floating_point_depth is between 0.0 and 1.0, of course.
Where floating_point_depth is between 0.0 and 1.0, of course.
===Copy filter registers===
=== Copy filter registers ===
{{regsimple | GX_BP_FILTER_0 | addr=0x01 | bits=24 | access = R/W}}
{{regsimple | GX_BP_FILTER_0 | addr=0x01 | bits=24 | access = R/W}}
{{regsimple | GX_BP_FILTER_1 | addr=0x02 | bits=24 | access = R/W}}
{{regsimple | GX_BP_FILTER_1 | addr=0x02 | bits=24 | access = R/W}}
Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.
Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.
===Vertical filter registers===
=== Vertical filter registers ===
{{reg24 | GX_BP_VFILTER_0 | addr = 0x53 | fields = 4 |
{{reg24 | GX_BP_VFILTER_0 | addr = 0x53 | fields = 4 |
|6 |6 |6 |6 |
|6 |6 |6 |6 |
|f3 |f2 |f1 |f0 |
|f3 |f2 |f1 |f0 |
}}
}}
{{reg24 | GX_BP_VFILTER_0 | addr = 0x54 | fields = 4 |
{{reg24 | GX_BP_VFILTER_1 | addr = 0x54 | fields = 4 |
|6 |6 |6 |6 |
|6 |6 |6 |6 |
|U |R/W |R/W |R/W |
|U |R/W |R/W |R/W |
}}
}}
==Beginning a copy==
== Beginning a copy ==
The following must take place to do a copy:
The following must take place to do a copy:
* Setup clear and z clear registers (optional)
* Setup clear and z clear registers (optional)