Changes

|}}

|}}

{{regdesc

{{regdesc

|BPE|Blitting processor enable

|BPE|Blitting processor enable (default=0?)

|GPLE|FIFO link enable (YAGCD says CP->PE?)

|GPLE|FIFO link enable (YAGCD says CP->PE?) (default=1)

|UFInt|FIFO underflow interrupt

|UFInt|FIFO underflow interrupt (default=0)

|OFInt|FIFO overflow interrupt

|OFInt|FIFO overflow interrupt (default=1)

|CPInt|Command Processor interrupt

|CPInt|Command Processor interrupt (default=0)

|FIFOE|FIFO read enable (disable while setting up)

|FIFOE|FIFO read enable (disable while setting up) (default=1)

}}

}}

===BP (blitting processor) registers===

===BP (blitting processor) registers===