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Hardware/GX/Blitting Processor (view source)
Revision as of 01:53, 21 March 2009
, 01:53, 21 March 2009The blitting processor deserves its own page
===BP (blitting processor) registers===
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
====EFB source registers====
One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:
* 0x49: coordinates to top left of rectangle in EFB that will be copied (packed format, unknown)
* 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)
====XFB destination registers====
The destination of the copy in the XFB is specified by the '''physical''' address of the XFB and the row stride (basically width of row, but no scaling appled).
{{regsimple | GX_BP_XFB_ADDR | addr=0x4B | bits=24 | access = R/W}}
* 0x4b: Address of destination (XFB). BEWARE: You only have 24 bits, which means your XFB must reside somewhere in the low 16MiB of RAM.
{{regsimple2 | GX_BP_XFB_STRIDE | addr=0x4D | bits=24 | split=10 | access = R/W}}
* 0x4d: Low 10 bits specify row stride of destination.
====Copy control register====
{{reg32 | GX_BP_COPY_CONTROL | addr = 0x52 | hifields = 2 | lofields = 4 |
|8 |8 |
|U |U |
|(register) | ||
|2|2 |1 | 11|
|U|W |R/W | U |
| |Begin copy |Clear enable | |
}}
* 0x52: This register starts a copy. Important bits:
* bit 10: Clear enable flag
* bits 12-15: Set all to 1 to enable a copy.
====Copy filter registers====
Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.
====Beginning a copy====
The following must take place to do a copy:
* Setup clear and z clear registers (optional)
* Set source and destination registers
* Write to display copy control register to begin a copy
* Set clear, z, and control registers again (what? doubt necessary, libogc GX is stupid)
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
====EFB source registers====
One can specify which part of the EFB is copied to the XFB or texture, using the following BP registers:
* 0x49: coordinates to top left of rectangle in EFB that will be copied (packed format, unknown)
* 0x4a: width and height-1 of rectangle to copy in EFB (again, unknown packed format)
====XFB destination registers====
The destination of the copy in the XFB is specified by the '''physical''' address of the XFB and the row stride (basically width of row, but no scaling appled).
{{regsimple | GX_BP_XFB_ADDR | addr=0x4B | bits=24 | access = R/W}}
* 0x4b: Address of destination (XFB). BEWARE: You only have 24 bits, which means your XFB must reside somewhere in the low 16MiB of RAM.
{{regsimple2 | GX_BP_XFB_STRIDE | addr=0x4D | bits=24 | split=10 | access = R/W}}
* 0x4d: Low 10 bits specify row stride of destination.
====Copy control register====
{{reg32 | GX_BP_COPY_CONTROL | addr = 0x52 | hifields = 2 | lofields = 4 |
|8 |8 |
|U |U |
|(register) | ||
|2|2 |1 | 11|
|U|W |R/W | U |
| |Begin copy |Clear enable | |
}}
* 0x52: This register starts a copy. Important bits:
* bit 10: Clear enable flag
* bits 12-15: Set all to 1 to enable a copy.
====Copy filter registers====
Registers 0x01-0x04 are used for tricks like antialiasing. For a plain copy (i.e. no antialiasing) set all for to 0x666666.
====Beginning a copy====
The following must take place to do a copy:
* Setup clear and z clear registers (optional)
* Set source and destination registers
* Write to display copy control register to begin a copy
* Set clear, z, and control registers again (what? doubt necessary, libogc GX is stupid)