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{{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}}
{{rla|0x0d80018c|32|HW_BOOT0|Maps boot0 {{check}}}}
{{rldrla|0x0d800194|32|HW_RESETS{{check}}|System resets / power{{check}}}}
{{rld|0x0d8001b4|32|HW_CLOCKS{{check}}|Clocking{{check}}}}
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{regdesc
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
}}
 
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
|5 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |
|U |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
| |A |B |HANG|D |E |F |G |H |I |DI2 |K ||
|1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |
|R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
|L |M |N |O |P |DI |R |S |T |U |PPC1|PPC2|V |SYS3|SYS2|SYS |
}}
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
{{regdesc
|HANG|System reset without recovery? Kills DI, sets slot LED on, hangs starlet...
|H|If cleared, kills EXI-based starlet experimental proxy.
|DI2|DI reset 2?
|K|If cleared, kills EXI-based starlet experimental proxy.
|P|If cleared, kills EXI-based starlet experimental proxy.
|DI|DI reset
|U|If cleared, kills EXI-based starlet experimental proxy.
|PPC1|PowerPC Reset 1 (release first)
|PPC2|PowerPC Reset 2 (release second)
|SYS3|System reset 3. Also seems to reboot system.
|SYS2|System reset 2. Also seems to reboot system.
|SYS|System reset. Set to zero to reboot system.
}}
{{hwstub}}

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