Changes

| hwdirq = 10, 11

| hwdirq = 10, 11

}}

}}

The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two sets of registers are provided, and the Broadway only has access to one set. This set accesses a configurable subset of the IO pins, which the Starlet can select.

The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two sets of registers are provided, and the Broadway only has access to one set. This set accesses a configurable subset of the IO pins, which the Starlet can select.

== Pin connections ==

== Pin connections ==

{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"

 

|- style="background-color: #ddd;"

"Direction" and "PPC access" are based on typical values that IOS<!--58--> assigns to the HW_GPIO_OWNER and HW_GPIO_DIR registers.

 

{| class="wikitable"

|-  

! Bit

! Bit

! Direction

! Direction

! Connection

! Connection

! Description

! Description

|-

|-

| 0 || IN || POWER || Power button input (pulse width limited; will not detect a held-down state).

| 0 || 0x000001 || {{yes|IN}} || {{no}}  || POWER || Power button input (pulse width limited; will not detect a held-down state).

|-

|-

| 1 || OUT || SHUTDOWN || Output high to turn system off (Power LED = red).

| 1 || 0x000002 || {{no|OUT}} || {{no}}  || SHUTDOWN || Output high to turn system off (Power LED = red).

|-

|-

| 2 || OUT || FAN || Fan power, active high.

| 2 || 0x000004 || {{no|OUT}} || {{no}}  || FAN || Fan power, active high.

|-

|-

| 3 || OUT || DC_DC || DC/DC converter power, active high (powers the Broadway?{{check}}). When off, also triggers the Yellow power LED.

| 3 || 0x000008 || {{no|OUT}} || {{no}}  || DC_DC || DC/DC converter power, active high (powers the Broadway?{{check}}). When off, also triggers the Yellow power LED.

|-

|-

| 4 || OUT || DI_SPIN || DI Spinup enable? Not sure{{check}}.

| 4 || 0x000010 || {{no|OUT}} || {{no}} || DI_SPIN || DI spinup disable. If clear, the drive attempts to spin up a disc when reset (if there is one in the drive). If set, the drive ignores a present disc when reset.

|-

|-

| 5 || OUT || SLOT_LED || Blue disc slot LED, active high.

| 5 || 0x000020 || {{no|OUT}} || {{yes}} || SLOT_LED || Blue disc slot LED, active high.

|-

|-

| 6 || IN || EJECT_BTN || Eject button (pulse width limited). Button press will also trigger the drive directly.

| 6 || 0x000040 || {{yes|IN}} || {{no}}  || EJECT_BTN || Eject button (pulse width limited). Button press will also trigger the drive directly.

|-

|-

| 7 || IN || SLOT_IN || Disc slot optical detector. High if disc in drive, disc being inserted, or disc still in slot after eject.

| 7 || 0x000080 || {{yes|IN}} || {{yes}} || SLOT_IN || Disc slot optical detector. High if disc in drive, disc being inserted, or disc still in slot after eject.  Temporarily low when inserting or exiting when the hole in the middle of the disc passes above the sensor.

|-

|-

| 8 || OUT || SENSOR_BAR || Sensor bar, active high.

| 8 || 0x000100 || {{no|OUT}} || {{yes}} || SENSOR_BAR || Sensor bar, active high.

|-

|-

| 9 || OUT || DO_EJECT || Pulse high to trigger a DI eject from software.

| 9 || 0x000200 || {{no|OUT}} || {{yes}} || DO_EJECT || Pulse high to trigger a DI eject from software.

|-

|-

| 10 || OUT || EEP_CS || [[Hardware/SEEPROM|SEEPROM]] Chip Select.

| 10 || 0x000400 || {{no|OUT}} || {{no}} || EEP_CS || [[Hardware/SEEPROM|SEEPROM]] Chip Select.

|-

|-

| 11 || OUT || EEP_CLK || [[Hardware/SEEPROM|SEEPROM]] Clock.

| 11 || 0x000800 || {{no|OUT}} || {{no}} || EEP_CLK || [[Hardware/SEEPROM|SEEPROM]] Clock.

|-

|-

| 12 || OUT || EEP_MOSI || Data to [[Hardware/SEEPROM|SEEPROM]].

| 12 || 0x001000 || {{no|OUT}} || {{no}} || EEP_MOSI || Data to [[Hardware/SEEPROM|SEEPROM]].

|-

|-

| 13 || IN || EEP_MISO || Data from [[Hardware/SEEPROM|SEEPROM]].

| 13 || 0x002000 || {{yes|IN}} || {{no}} || EEP_MISO || Data from [[Hardware/SEEPROM|SEEPROM]].

|-

|-

| 14 || OUT || AVE_SCL || [[Hardware/AVE|A/V Encoder]] I²C Clock.

| 14 || 0x004000 || {{no|OUT}} || {{yes}} || AVE_SCL || [[Hardware/AV Encoder|A/V Encoder]] I²C Clock.

|-

|-

| 15 || I/O || AVE_SDA || [[Hardware/AVE|A/V Encoder]] I²C Data (has an external pull-up, so you should only drive it low).

| 15 || 0x008000 || {{no|I/O}} || {{yes}} || AVE_SDA || [[Hardware/AV Encoder|A/V Encoder]] I²C Data (has an external pull-up, so you should only drive it low).

|-

|-

| 16 || OUT || DEBUG0 || [[Debug port|Debug Testpoint]] TP221.

| 16 || 0x010000 || {{no|OUT}} || {{no}}  || DEBUG0 || [[Debug port|Debug Testpoint]] TP221.

|-

|-

| 17 || OUT || DEBUG1 || [[Debug port|Debug Testpoint]] TP222.

| 17 || 0x020000 || {{no|OUT}} || {{no}}  || DEBUG1 || [[Debug port|Debug Testpoint]] TP222.

|-

|-

| 18 || OUT || DEBUG2 || [[Debug port|Debug Testpoint]] TP223.

| 18 || 0x040000 || {{no|OUT}} || {{no}}  || DEBUG2 || [[Debug port|Debug Testpoint]] TP223.

|-

|-

| 19 || OUT || DEBUG3 || [[Debug port|Debug Testpoint]] TP224.

| 19 || 0x080000 || {{no|OUT}} || {{no}}  || DEBUG3 || [[Debug port|Debug Testpoint]] TP224.

|-

|-

| 20 || OUT || DEBUG4 || [[Debug port|Debug Testpoint]] TP225.

| 20 || 0x100000 || {{no|OUT}} || {{no}}  || DEBUG4 || [[Debug port|Debug Testpoint]] TP225.

|-

|-

| 21 || OUT || DEBUG5 || [[Debug port|Debug Testpoint]] TP226.

| 21 || 0x200000 || {{no|OUT}} || {{no}}  || DEBUG5 || [[Debug port|Debug Testpoint]] TP226.

|-

|-

| 22 || OUT || DEBUG6 || [[Debug port|Debug Testpoint]] TP219.

| 22 || 0x400000 || {{no|OUT}} || {{no}}  || DEBUG6 || [[Debug port|Debug Testpoint]] TP219.

|-

|-

| 23 || OUT || DEBUG7 || [[Debug port|Debug Testpoint]] TP220.

| 23 || 0x800000 || {{no|OUT}} || {{no}} || DEBUG7 || [[Debug port|Debug Testpoint]] TP220.

 

{{reglist|Hollywood GPIOs}}

{{rla|0x0d8000c0|32|HW_GPIOB_OUT|GPIO Outputs (Broadway access)}}

{{rla|0x0d8000c4|32|HW_GPIOB_DIR|GPIO Direction (Broadway access)}}

{{rla|0x0d8000c8|32|HW_GPIOB_IN|GPIO Inputs (Broadway access)}}

{{rla|0x0d8000cc|32|HW_GPIOB_INTLVL|GPIO Interrupt Levels (Broadway access)}}

|}

|}

This register contains the output value for all pins. These only take effect if the pin is configured as an output.

This register contains the output value for all pins. These only take effect if the pin is configured as an output.

----

----

{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e0|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}

A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.

A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.

----

----

{{regsimple2|HW_GPIO_IN|addr=0x0d8000e0|bits=32|split=24|access=R}}

{{regsimple2|HW_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}

This register can be read to obtain the current input value of the GPIO pins.

This register can be read to obtain the current input value of the GPIO pins.

----

----

{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000e0|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}

Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.

Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.

----

----

Only the bits set in this register propagate their interrupts to the master [[Hardware/Hollywood IRQs|Hollywood GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#HW_GPIO_INTFLAG|HW_GPIO_INTFLAG]]. Note: Pins configured for Broadway access do not generate Hollywood IRQ #11. Instead, they generate Hollywood IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.

Only the bits set in this register propagate their interrupts to the master [[Hardware/Hollywood IRQs|Hollywood GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#HW_GPIO_INTFLAG|HW_GPIO_INTFLAG]]. Note: Pins configured for Broadway access do not generate Hollywood IRQ #11. Instead, they generate Hollywood IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.

----

----

{{regsimple2|HW_GPIO_INMIR|addr=0x0d8000f8|bits=32|split=24|access=R}}

{{regsimple2|HW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}

This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. {{check}}

This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.  

----

----

{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}

{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}

{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}

{{regsimple2|HW_GPIOB_INMIR|addr=0x0d8000d8|bits=32|split=24|access=R}}

{{regsimple2|HW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}

These registers operate identically to their HW_GPIO counterparts above, but they only control the pins which have their respective [[#HW_GPIO_OWNER|HW_GPIO_OWNER]] bits set to 1. They can be accessed by the Broadway as well as the Starlet. The master interrupt feeds to the [[Hardware/Hollywood IRQs|Hollywood GPIOB interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the GPIOB registers are already masked with the HW_GPIO_OWNER register.

These registers operate identically to their HW_GPIO counterparts above, but they only control the pins which have their respective [[#HW_GPIO_OWNER|HW_GPIO_OWNER]] bits set to 1. They can be accessed by the Broadway as well as the Starlet. The master interrupt feeds to the [[Hardware/Hollywood IRQs|Hollywood GPIOB interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the GPIOB registers are already masked with the HW_GPIO_OWNER register.

When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB registers have to that data.

When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB registers have to that data.