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{{hwstub}}
The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two full sets of registers are provided, and the Broadway only has access to one halfset. Each pin can be assigned to one This set accesses a configurable subset of the two sets of registersIO pins, which lets the Starlet control which pins only it can control, and which pins the Broadway can use tooselect.
== Pin connections ==
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{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high (or on the rising edge?{{check}}). A zero causes the opposite behavior.
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{{regsimple2|HW_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIO_INTLVL register, then the corresponding bit in HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
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{{regsimple2|HW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master [[Hardware/Hollywood IRQs|Hollywood GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#HW_GPIO_INTFLAG|HW_GPIO_INTFLAG]]. Note: Pins configured for Broadway access do not generate Hollywood IRQ #11. Instead, they generate Hollywood IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.
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{{regsimple2|HW_GPIO_INMIR|addr=0x0d8000f8|bits=32|split=24|access=R/W}}This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. {{check}}
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{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
This register configures which pins are can be controlled with HW_GPIO registers vs by the HW_GPIOB registers. A one bit configures the pin for control via the HW_GPIOB registers, and enables access which lets it be accessed by the Broadway. A zero bit restricts access to the HW_GPIO registers, which are Starlet-only. The HW_GPIO registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB registers if the corresponding bit is set in the HW_GPIO_OWNER register.
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{{regsimple2|HW_GPIOB_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INMIR|addr=0x0d8000d8|bits=32|split=24|access=R/W}}These registers operate identically to their HW_GPIO counterparts above, but they only control the pins which have their respective [[#HW_GPIO_OWNER|HW_GPIO_OWNER]] bits set to 1. They can be accessed by the Broadwayas well as the Starlet. The master interrupt feeds to the [[Hardware/Hollywood IRQs|Hollywood GPIOB interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the GPIOB registers are already masked with the HW_GPIO_OWNER register. When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB registers have to that data.

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