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{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
{{rld|0x0d800014|32|HW_ALARM}}
{{rld|0x0d800014|32|HW_ALARM}}
{{rld|0x0d800038|32|HW_IRQFLAG|[[Hardware/Hollywood IRQs|Hollywood IRQ control]]|drs=2}}
{{rld|0x0d800038|32|HW_PPCIRQFLAG|[[Hardware/Hollywood IRQs|Hollywood IRQ controller]]|drs=4}}
{{rld|0x0d80003c|32|HW_IRQENABLE}}
{{rld|0x0d80003c|32|HW_PPCIRQMASK}}
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
{{rld|0x0d800038|32|HW_MEMIRR|Memory control / SRAM bank swap{{check}}}}
{{rld|0x0d800038|32|HW_MEMIRR|Memory control / SRAM bank swap{{check}}}}
{{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
{{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
{{reg32 | HW_EXICTRL | addr = 0x0d800070 | hifields = 1 | lofields = 2 |
{{reg32 | HW_EXICTRL | addr = 0x0d800070 | hifields = 1 | lofields = 2 |
|16 |
|16 |
|U |
|? |
| ||
| ||
|15|1 |
|15|1 |
|U |R/W |
|? |R/W |
| |EXI ||
| |EXI ||
}}
}}
{{reg32 | HW_DIFLAGS | addr = 0x0d800180 | hifields = 3 | lofields = 1 |
{{reg32 | HW_DIFLAGS | addr = 0x0d800180 | hifields = 3 | lofields = 1 |
|11 |1 |4 |
|11 |1 |4 |
|U?|R/W | U? |
|? |R/W |? |
| |PPCBOOT| ||
| |PPCBOOT| ||
|16 |
|16 |
|U? |
|? |
| |
| |
}}
}}
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 3 |
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 3 |
|16 |
|16 |
|U? |
|? |
| ||
| ||
|3 |1 |12 |
|3 |1 |12 |
|U?|R/W | U? |
|?|R/W | ? |
| |BOOT0| |
| |BOOT0| |
}}
}}
This register at least control the boot0 memory mapping.
This register at least control the boot0 memory mapping.
{{regdesc
{{regdesc
|BOOT0|Enable boot0 mapping to either x'fff0_0000 or x'ffff_0000 depending on HW_MEMMIRR
|BOOT0|Enable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
}}
}}
{{hwstub}}
{{hwstub}}