Changes

==GX FIFO==

==GX FIFO==

Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

===BP registers===

===BP (blitting processor) registers===

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bits of something.

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the low 8 bits are the register, and the high 24 bits are the register value.

===CP (command processor) registers===

===CP (command processor) registers===

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.

===XF (transform) registers===

===XF (transform) registers===

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.