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fix INMIR registers to STRAPS
| len = 0x40
| bits = 32
| armirq hwdirq = 10, 11
}}
{{hwstub}}
The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two full sets of registers are provided, and the Broadway only has access to one halfset. Each pin can be assigned to one This set accesses a configurable subset of the two sets of registersIO pins, which lets the Starlet control which pins only it can control, and which pins the select. == Register list =={{reglist|Hollywood GPIOs}}{{rla|0x0d8000c0|32|HW_GPIOB_OUT|GPIO Outputs (Broadway access)}}{{rla|0x0d8000c4|32|HW_GPIOB_DIR|GPIO Direction (Broadway access)}}{{rla|0x0d8000c8|32|HW_GPIOB_IN|GPIO Inputs (Broadway access)}}{{rla|0x0d8000cc|32|HW_GPIOB_INTLVL|GPIO Interrupt Levels (Broadway access)}}{{rla|0x0d8000d0|32|HW_GPIOB_INTFLAG|GPIO Interrupt Flags (Broadway access)}}{{rla|0x0d8000d4|32|HW_GPIOB_INTMASK|GPIO Interrupt Masks (Broadway access)}}{{rla|0x0d8000d8|32|HW_GPIOB_STRAPS|GPIO Straps (Broadway can use too.access)}}{{rla|0x0d8000dc|32|HW_GPIO_ENABLE|GPIO Enable (Starlet only)}}{{rla|0x0d8000e0|32|HW_GPIO_OUT|GPIO Outputs (Starlet only)}}{{rla|0x0d8000e4|32|HW_GPIO_DIR|GPIO Direction (Starlet only)}}{{rla|0x0d8000e8|32|HW_GPIO_IN|GPIO Inputs (Starlet only)}}{{rla|0x0d8000ec|32|HW_GPIO_INTLVL|GPIO Interrupt Levels (Starlet only)}}{{rla|0x0d8000f0|32|HW_GPIO_INTFLAG|GPIO Interrupt Flags (Starlet only)}}{{rla|0x0d8000f4|32|HW_GPIO_INTMASK|GPIO Interrupt Masks (Starlet only)}}{{rla|0x0d8000f8|32|HW_GPIO_STRAPS|GPIO Straps (Starlet only)}}{{rla|0x0d8000fc|32|HW_GPIO_OWNER|GPIO Owner Select (Starlet only)}}|}
== Pin connections ==
{| style="Direction" and "PPC access"border: 1px solid #bbb; borderare based on typical values that IOS<!-collapse: collapse; background-color: #eef; padding: 058--> assigns to the HW_GPIO_OWNER and HW_GPIO_DIR registers.2em 0.2em 0.2em 0.2em;" border="1" cellpadding {| class="0.2emwikitable"|- style="background-color: #ddd;"
! Bit
! Mask
! Direction
! PPC access
! Connection
! Description
|-
| 0 || 0x000001 || {{yes| IN }} || {{no}} || POWER || Power button input (pulse width limited; will not detect a held-down state).
|-
| 1 || 0x000002 || {{no| OUT }} || {{no}} || SHUTDOWN || Output high to turn system off (Power LED = red).
|-
| 2 || 0x000004 || {{no| OUT }} || {{no}} || FAN || Fan power, active high.
|-
| 3 || 0x000008 || {{no| OUT }} || {{no}} || DC_DC || DC/DC converter power, active high (powers the Broadway?{{check}}). When off, also triggers the Yellow power LED.
|-
| 4 || OUT 0x000010 ||{{no| DI_SPIN OUT}} || DI Spinup enable? Not sure{{checkno}} || DI_SPIN || DI spinup disable. If clear, the drive attempts to spin up a disc when reset (if there is one in the drive). If set, the drive ignores a present disc when reset.
|-
| 5 || 0x000020 || {{no| OUT }} || {{yes}} || SLOT_LED || Blue disc slot LED, active high.
|-
| 6 || 0x000040 || {{yes| IN }} || {{no}} || EJECT_BTN || Eject button (pulse width limited). Button press will also trigger the drive directly.
|-
| 7 || 0x000080 || {{yes| IN }} || {{yes}} || SLOT_IN || Disc slot optical detector. High if disc in drive, disc being inserted, or disc still in slot after eject. Temporarily low when inserting or exiting when the hole in the middle of the disc passes above the sensor.
|-
| 8 || 0x000100 || {{no| OUT }} || {{yes}} || SENSOR_BAR || Sensor bar, active high.
|-
| 9 || 0x000200 || {{no| OUT }} || {{yes}} || DO_EJECT || Pulse high to trigger a DI eject from software.
|-
| 10 || 0x000400 || {{no| OUT }} || {{no}} || EEP_CS || [[Hardware/SEEPROM|SEEPROM]] Chip Select.
|-
| 11 || 0x000800 || {{no| OUT }} || {{no}} || EEP_CLK || [[Hardware/SEEPROM|SEEPROM]] Clock.
|-
| 12 || 0x001000 || {{no| OUT }} || {{no}} || EEP_MOSI || Data to [[Hardware/SEEPROM|SEEPROM]].
|-
| 13 || 0x002000 || {{yes| IN }} || {{no}} || EEP_MISO || Data from [[Hardware/SEEPROM|SEEPROM]].
|-
| 14 || 0x004000 || {{no| OUT }} || {{yes}} || AVE_SCL || [[Hardware/AVEAV Encoder|A/V Encoder]] I²C Clock.
|-
| 15 || 0x008000 || {{no| I/O }} || {{yes}} || AVE_SDA || [[Hardware/AVEAV Encoder|A/V Encoder]] I²C Data (has an external pull-up, so you should only drive it low).
|-
| 16 || 0x010000 || {{no| OUT }} || {{no}} || DEBUG0 || [[Debug port| Debug Testpoint ]] TP221.
|-
| 17 || 0x020000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG1 || [[Debug port| Debug Testpoint ]] TP222.
|-
| 18 || 0x040000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG2 || [[Debug port| Debug Testpoint ]] TP223.
|-
| 19 || 0x080000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG3 || [[Debug port| Debug Testpoint ]] TP224.
|-
| 20 || 0x100000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG4 || [[Debug port| Debug Testpoint ]] TP225.
|-
| 21 || 0x200000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG5 || [[Debug port| Debug Testpoint ]] TP226.
|-
| 22 || 0x400000 || {{no| OUT }} || DEBUG0 {{no}} || DEBUG6 || [[Debug port| Debug Testpoint ]] TP219.
|-
| 23 || OUT || DEBUG0 || Debug Testpoint TP220|}  insertion.| 0 || OUT || SENSOR_BAR 0x800000 || Sensor bar power, active highPin Dir Owner Description 0 IN ARM Power Button (pulse on press) 1 OUT ARM Shutdown (write 1 for poweroff to red mode) 2 OUT ARM Fan 3 OUT ARM DC-DC converter (write 0 to turn LED yellow and presumably shut down PPC) 4 OUT ARM DI Spinup Enable (maybe; unsure) 5 OUT varies Slot LED 6 IN ARM Eject button (pulse on press) - also triggers DI eject in hardware 7 IN PPC Disc slot front insertion detector - also triggers DI insert in hardware 8 OUT PPC Sensor Bar 9 OUT PPC DI Eject (write 1 to trigger) 10 OUT ARM SEEPROM CS 11 OUT ARM SEEPROM CLK 12 OUT ARM SEEPROM MOSI 13 IN ARM SEEPROM MISO 14 OUT PPC Video Encoder SCL 15 I/O PPC Video Encoder SDA 16 OUT ARM Debug port bit 0 / TP221 17 OUT ARM Debug port bit 1 / TP222 18 OUT ARM Debug port bit 2 / TP223 19 OUT ARM Debug port bit 3 / TP224 20 OUT ARM Debug port bit 4 / TP225 21 OUT ARM Debug port bit 5 / TP226 22 OUT ARM Debug port bit 6 / TP219 23 OUT ARM Debug port bit 7 / TP220|} == Register list =={{reglistno|Hollywood GPIOsOUT}}{{rla|0x0d8000c0|32|HW_GPIOB_OUT|GPIO Outputs (Broadway access)}}{{rla|0x0d8000c4|32|HW_GPIOB_DIR|GPIO Direction (Broadway access)no}}{{rla |0x0d8000c8|32DEBUG7 |HW_GPIOB_IN|GPIO Inputs (Broadway access)}}{{rla[[Debug port|0x0d8000cc|32|HW_GPIOB_INTLVL|GPIO Interrupt Levels (Broadway access)}}{{rla|0x0d8000d0|32|HW_GPIOB_INTFLAG|GPIO Interrupt Flags (Broadway access)}}{{rla|0x0d8000d4|32|HW_GPIOB_INTMASK|GPIO Interrupt Masks (Broadway access)}}{{rla|0x0d8000d8|32|HW_GPIOB_INMIR|GPIO Input Mirror (Broadway access)}}{{rla|0x0d8000dc|32|HW_GPIO_ENABLE|GPIO Enable}}{{rla|0x0d8000e0|32|HW_GPIO_OUT|GPIO Outputs (Starlet only)}}{{rla|0x0d8000e4|32|HW_GPIO_DIR|GPIO Direction (Starlet only)}}{{rla|0x0d8000e8|32|HW_GPIO_IN|GPIO Inputs (Starlet only)}}{{rla|0x0d8000ec|32|HW_GPIO_INTLVL|GPIO Interrupt Levels (Starlet only)}}{{rla|0x0d8000f0|32|HW_GPIO_INTFLAG|GPIO Interrupt Flags (Starlet only)}}{{rla|0x0d8000f4|32|HW_GPIO_INTMASK|GPIO Interrupt Masks (Starlet only)}}{{rla|0x0d8000f8|32|HW_GPIO_INMIR|GPIO Input Mirror (Starlet only)}}{{rla|0x0d8000fc|32|HW_GPIO_OWNER|GPIO Owner Select}}Debug Testpoint]] TP220.
|}
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
----
{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e00x0d8000e4|bits=32|split=24|access=R/W}}
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
----
{{regsimple2|HW_GPIO_IN|addr=0x0d8000e00x0d8000e8|bits=32|split=24|access=R}}
This register can be read to obtain the current input value of the GPIO pins.
----
{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000e00x0d8000ec|bits=32|split=24|access=R/W}}Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high (or on the rising edge?{{check}}). A zero causes the opposite behavior.
----
{{regsimple2|HW_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIO_INTLVL register, then the corresponding bit in HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
----
{{regsimple2|HW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master Starlet [[Hardware/Hollywood IRQs|Hollywood GPIO interrupt ]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#HW_GPIO_INTFLAG|HW_GPIO_INTFLAG]]. Note: Pins configured for Broadway access do not generate Hollywood IRQ #11. Instead, they generate Hollywood IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.
----
{{regsimple2|HW_GPIO_INMIRHW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R/W}}This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. {{check}}Writes do not seem possible.
----
{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
This register configures which pins are can be controlled with HW_GPIO registers vs by the HW_GPIOB registers. A one bit configures the pin for control via the HW_GPIOB registers, and enables access which lets it be accessed by the Broadway. A zero bit restricts access to the HW_GPIO registers, which are Starlet-only. The HW_GPIO registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB registers if the corresponding bit is set in the HW_GPIO_OWNER register.
----
{{regsimple2|HW_GPIOB_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INMIRHW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R/W}}These registers operate identically to their HW_GPIO counterparts above, but they only control the pins which have their respective [[#HW_GPIO_OWNER|HW_GPIO_OWNER]] bits set to 1. They can be accessed by the Broadway, although their as well as the Starlet. The master interrupt feeds to the [[Hardware/Hollywood IRQs|Hollywood GPIOB interrupt ]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK) , with an implicit AND with HW_GPIO_OWNER since the GPIOB registers are already masked with the HW_GPIO_OWNER register. When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB registers. There is mapped only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB registers have to Starlet IRQ #10that data.

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