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No change in size ,  20:12, 27 February 2009
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INMIR|addr=0x0d8000d8|bits=32|split=24|access=R/W}}
These registers operate identically to their HW_GPIO counterparts above, but they control the pins which have their respective {{[[#HW_GPIO_OWNER|HW_GPIO_OWNER}} ]] bits set to 1. They can be accessed by the Broadway, although their interrupt (HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK) is mapped to Starlet IRQ #10.

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