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Line 8: − {| border="1"+ − ! address !! function !! contents/example+ − |-+ − |0x0D8000C0||GPIO || probably data: 0x200 for eject; 0x100 sensor bar enable; 0x20 for tray led+ − |-+ − ||0x0D8000C4||GPIO || probably direction+ − |-+ − ||0x0D8000DC||???+ − |-+ − ||0x0D8000E0||GPIO || 0x08 -- set to enable DC/DC converter, + − |-+ − ||0x0D8000E1||GPIO || + − |-+ − ||0x0D8000E2||GPIO || debug / "POST" port -- connected to 8 testpads. boot0 / 1 / 2 output simple codes to indicate boot status.+ − |-+ − ||0x0D8000E3||GPIO || + − |-+ − ||0x0D8000E4||GPIO || probably direction+ − |-+ − ||0x0D8000EC||???+ − |- − ||0x0D8000F0|| ? typical value is 0x0070FFF6; pressing the POWER button will set the 0x1 bit − |- − − − ||0x0D8000FC||??? − − ||0x0D800100||??? − − ||0x0D80010C||??? − − ||0x0D800110||??? − − ||0x0D800114||??? − − − − − − ||0x0D800120||??? − − ||0x0D800130||??? − − ||0x0D800134||??? − − ||0x0D800138||??? − − ||0x0D800180||??? || set 0x40 for legacy DI; 0x100000 set after loadEXI (boot code) − − ||0x0D800188||??? − − ||0x0D80018C||??? − − ||0x0D800190||??? || involved in DSKPLL init − |- − ||0x0D800194||??? || 0x400 is DI reset (low active) / involved in DSKPLL init − − − |- − ||0x0D8001B0||??? || ACRPLLSYS − |- − ||0x0D8001B0||??? || ACRPLLSYSEXT − |- − ||0x0D8001B8||??? || involved in DSKPLL init − |- − ||0x0D8001BC||??? − |- − ||0x0D8001C0||??? − |- − ||0x0D8001DC||??? || set to 0x00FFFFFF as part of "interface / subsytem powerup" − |- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
no edit summary
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{{hwstub}}
{{hwstub}}
The Hollywood chipset includes 24 general purpose I/O lines with interrupt capability. Two full sets of registers are provided, and the Broadway only has access to one half. Each pin can be assigned to one of the two sets of registers, which lets the Starlet control which pins only it can control, and which pins the Broadway can use too.
{{reglist|Hollywood GPIOs}}
{{rla|0x0d8000c0|32|HW_GPIOB_OUT}}
{{rla|0x0d8000c4|32|HW_GPIOB_DIR}}
{{rla|0x0d8000c8|32|HW_GPIOB_IN}}
{{rla|0x0d8000cc|32|HW_GPIOB_INTLVL}}
{{rla|0x0d8000d0|32|HW_GPIOB_INTFLAG}}
{{rla|0x0d8000d4|32|HW_GPIOB_INTMASK}}
{{rla|0x0d8000d8|32|HW_GPIOB_INMIR}}
{{rla|0x0d8000dc|32|HW_GPIO_ENABLE}}
{{rla|0x0d8000e0|32|HW_GPIO_OUT}}
{{rla|0x0d8000e4|32|HW_GPIO_DIR}}
{{rla|0x0d8000e8|32|HW_GPIO_IN}}
{{rla|0x0d8000ec|32|HW_GPIO_INTLVL}}
{{rla|0x0d8000f0|32|HW_GPIO_INTFLAG}}
{{rla|0x0d8000f4|32|HW_GPIO_INTMASK}}
{{rla|0x0d8000f8|32|HW_GPIO_INMIR}}
{{rla|0x0d8000fc|32|HW_GPIO_OWNER}}
||0x0D8000F4||???
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||0x0D800118||???
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||0x0D80011C||???
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||0x0D800198||??? || set to 0x00FFFFFF as part of "interface / subsytem powerup"
|}
|}
== Register Description ==
{{regsimple2|HW_GPIO_ENABLE|bits=32|split=24|access=R/W}}
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
----
{{regsimple2|HW_GPIO_OUT|bits=32|split=24|access=R/W}}
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
----
{{regsimple2|HW_GPIO_DIR|bits=32|split=24|access=R/W}}
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
----
{{regsimple2|HW_GPIO_IN|bits=32|split=24|access=R}}
This register can be read to obtain the current input value of the GPIO pins.
----
{{regsimple2|HW_GPIO_INTLVL|bits=32|split=24|access=R/W}}
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high (or on the rising edge?{{check}}). A zero causes the opposite behavior.
----
{{regsimple2|HW_GPIO_INTFLAG|bits=32|split=24|access=R/Z}}
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero.
----
{{regsimple2|HW_GPIO_INTMASK|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master Starlet GPIO interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#HW_GPIO_INTFLAG|HW_GPIO_INTFLAG]].
----
{{regsimple2|HW_GPIO_INMIR|bits=32|split=24|access=R/W}}
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. {{check}}
----
{{regsimple2|HW_GPIO_OWNER|bits=32|split=24|access=R/W}}
This register configures which pins are controlled with HW_GPIO registers vs HW_GPIOB registers. A one bit configures the pin for control via the HW_GPIOB registers, and enables access by the Broadway. A zero bit restricts access to the HW_GPIO registers, which are Starlet-only.
----
{{regsimple2|HW_GPIOB_OUT|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_DIR|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_IN|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOB_INTLVL|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INTFLAG|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INTMASK|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INMIR|bits=32|split=24|access=R/W}}
These registers operate identically to their HW_GPIO counterparts above, but they control the pins which have their respective {{#HW_GPIO_OWNER|HW_GPIO_OWNER}} bits set to 1. They can be accessed by the Broadway, although their interrupt (HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK) is mapped to Starlet IRQ #10.