Broadway/Registers: Difference between revisions
< Broadway
added rest of GQRs |
No edit summary |
||
| Line 1: | Line 1: | ||
{{Orphan}} | |||
On this page you can find a description of some of the registers available in the "Broadway" CPU. | On this page you can find a description of some of the registers available in the "Broadway" CPU. | ||
The "Broadway" CPU is an enhanced version of the "Gekko" CPU developed for the Nintendo GameCube videoconsole, which is based on the PowerPC 750CXe CPU design. | The "Broadway" CPU is an enhanced version of the "Gekko" CPU developed for the Nintendo GameCube videoconsole, which is based on the PowerPC 750CXe CPU design. | ||
Revision as of 10:19, 22 February 2008
 |
This article is an orphan, as few or no other articles link to it. Please introduce links to this page from other articles related to it. |
On this page you can find a description of some of the registers available in the "Broadway" CPU. The "Broadway" CPU is an enhanced version of the "Gekko" CPU developed for the Nintendo GameCube videoconsole, which is based on the PowerPC 750CXe CPU design.
Special Purpose Registers (SPRs)
Most of these registers are already present on 750CX or Gekko. Others seem to be new (like HID4).
| Name | Number | Description |
| GQR0 | 912 (0x390) | Graphics Quantization Register 0 |
| GQR1 | 913 (0x391) | Graphics Quantization Register 1 |
| GQR2 | 914 (0x392) | Graphics Quantization Register 2 |
| GQR3 | 915 (0x393) | Graphics Quantization Register 3 |
| GQR4 | 916 (0x394) | Graphics Quantization Register 4 |
| GQR5 | 917 (0x395) | Graphics Quantization Register 5 |
| GQR6 | 918 (0x396) | Graphics Quantization Register 6 |
| GQR7 | 919 (0x397) | Graphics Quantization Register 7 |
| HID0 | 1008 (0x3F0) | Hardware Implementation-Dependent register 0 |
| HID1 | 1009 (0x3F1) | Hardware Implementation-Dependent register 1 |
| HID2 | 920 (0x398) | Hardware Implementation-Dependent register 2 |
| HID4 | 1011 (0x3F3) | Hardware Implementation-Dependent register 4 |
| L2CR | 1017 (0x3F9) | Layer 2 cache Control Register |
| MMCR0 | 952 (0x3B8) | Monitor Mode Control Register 0 |
| MMCR1 | 956 (0x3BC) | Monitor Mode Control Register 1 |
| PMC1 | 953 (0x3B9) | Performance Monitor Counter register 1 |
| PMC2 | 954 (0x3BA) | Performance Monitor Counter register 2 |
| PMC3 | 957 (0x3BD) | Performance Monitor Counter register 3 |
| PMC4 | 958 (0x3BE) | Performance Monitor Counter register 4 |
| WPAR | 921 (0x399) | Write-gather Pipe Address Register |
| ... | ... | ... |
HID4
Bit 31 (most significant bit) is H4A (unknown purpose). The "Broadway" CPU seems to have a bug which makes unreliable to clear this bit, as noted in some strings present in games.