40
edits
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Add physical base addresses.
Line 3:
Line 3:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Start Address'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Start Address'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''End Address'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''End Address'''
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Physical Address'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Size'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Size'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Description'''
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Description'''
Line 9:
Line 10:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x80000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x80000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x817FFFFF
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x817FFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Cached)
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Cached)
Line 15:
Line 17:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xC0000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xC0000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xC17FFFFF
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xC17FFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Uncached)
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Uncached)
Line 21:
Line 24:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x90000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x90000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x93FFFFFF
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x93FFFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Cached)
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Cached)
Line 27:
Line 31:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xD0000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xD0000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xD3FFFFFF
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xD3FFFFFF
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Uncached)
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Uncached)
Line 33:
Line 38:
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xCD000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xCD000000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xCD008000
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xCD008000
+| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers