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| hwdirq = 0,10,11,17,30,31,...{{check}}
The Hollywood chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the PowerPC. Address bit 23 (0x00800000; aka AHB_TRUSTED_OFFSET) controls the permission: if it is set, then the registers are accessed with Starlet permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
See also the MINI source code, especially [;a=blob;f=hollywood.h hollywood.h].
|SM|IOUEN; Enables the SRAM mirror at 0xfffe0000 when set
|U3|AHPEN; Set/cleared by syscall (0x54 in IOS58; ), maybe related to it's for enable HW_AHBPROT?
|C|FLAEN (Flash/NAND engine); Explicitly set by boot0/boot1 before using NAND/AES/SHA
|B|SHAEN (SHA-1 engine); Explicitly set by boot0/boot1 before using NAND/AES/SHA
| |PPC Rights| ||
This register controls controls the hardware rights (access to various engines/interfaces) for both the PPC (Broadway) and IOP (Starlet/IOS). By default, only Starlet/IOS can write to this register. You are able to freely write to the unused bits. If a TMD has it's access right bit flipped high, syscall (540x54) is called from IOS and the register gets logically OR'd with the value of 0x80000DFE, thus giving PPC access to every engine/interface. Link -
Flip a bit high to enable access.
|K| PPCKERN; PPC Kernel? Flipped high from syscall (540x54)
|IOS Rights| Hardware/Interface Rights for IOS
|PPC RIghts| Hardware/Interface Rights for PPC|


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