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Added in register details for HW_AHBPROT
{{rld|0x0d80005c|32|HW_DBGINTEN}}
{{rla|0x0d800060|32|HW_SRNPROT|Probably bus control; includes the SRAM bank swap }}
{{rldrla|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}}
{{rld|0x0d800068|32|HW_I2CIOPINTEN}}
{{rld|0x0d80006c|32|HW_I2CIOPINTSTS}}
|A|AESEN (AES engine); Explicitly set by boot0/boot1 before using NAND/AES/SHA
}}
 
{{reg32 | HW_AHBPROT | addr = 0x0d800064 | hifields = 4 | lofields = 3 |
|1 |6|8 |1|
|R/W|U|R/W |U|
|K | |IOS Rights| ||
|7|8 |1|
|U|R/W |U|
| |PPC Rights| ||
}}
This register controls controls the hardware rights (access to various engines/interfaces) for both the PPC (Broadway) and IOP (Starlet/IOS). Only Starlet/IOS can write to this register. You are able to freely write to the unused bits. If a TMD has it's access right bit flipped high, syscall (54) is called from IOS and the register gets logically OR'd with the value of 0x80000DFE, thus giving PPC access to every engine/interface. Link - https://hackmii.com/2009/08/of-tmds-and-hardware/
 
Flip a bit high to enable access.
 
{{regdesc
|K| PPCKERN; PPC Kernel? Flipped high from syscall (54)
|IOS Rights| Hardware/Interface Rights for IOS
|PPC RIghts| Hardware/Interface Rights for PPC|
}}
Bit Mapping (listed in plain text format due to field limitations of this wiki template):
*Bits 24 & 8 = SD Interface #1
*Bits 23 & 7 = SD Interface #0
*Bits 22 & 6 = Open Host Interface #1
*Bits 21 & 5 = Open Host Interface #0
*Bits 20 & 4 = Enhanced Host Interface
*Bits 19 & 3 = SHA-1 Engine
*Bits 18 & 2 = AES Engine
*Bits 17 & 1 = Flash (NAND) Engine
 
{{reg32 | HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 |
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