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{{rld|0x0d800058|32|HW_DBGINTSTS}}
{{rld|0x0d80005c|32|HW_DBGINTEN}}
{{rla|0x0d800060|32|HW_MEMIRRHW_SRNPROT|Memory Probably bus control / ; includes the SRAM bank swap ("HW_SRNPROT"){{check}}}}
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}}
{{rla|0x0d800070|32|HW_EXICTRLHW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other ("HW_AIP_PROT") {{check}}; probably related to Flipper interface compatibility}}{{rldrla|0x0d800074|32|HW_AIP_IOCTRLHW_AIPIOCTRL|??Probably related to Flipper interface compatibility/bus control}}
{{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}}
{{rld|0x0d800084|32|HW_USBDBG1}}
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
{{rla|0x0d800180|32|HW_COMPAT| Some DI stuff and boot code and {{check}}}}
{{rlarld|0x0d800184|32|HW_UNKFLAGSHW_RESET_AHB|{{check}}}}
{{rld|0x0d800188|32|HW_SPARE0|?}}
{{rla|0x0d80018c|32|HW_BOOT0|(ACR_SPARE1) Controls boot0 mapping? {{check}}}}
}}
{{reg32 | HW_MEMIRR HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 |
|16 |
|? |
}}
{{reg32 | HW_EXICTRL HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 |
|16 |
|? |
|11|1 |3|1 |
|? |R/W|?|R/W |
| |DI | |EXI ENAHBIOPI ||
}}
This register controls at least the current EXI status. It's probably related to bus control/GC compatibility.
{{regdesc
|DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}}
|EXIENAHBIOPI|enable "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI.
}}
 
{{reg32 | HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 |
|16 |
|? |
| ||
|15|1 |
|? |? |
| |ENAHBIOMEM ||
}}
This register is probably related to bus control/GC compatibility.
{{regdesc
|ENAHBIOMEM| This bit is named in IOSv3.
}}
 
{{reg32 | HW_COMPAT| addr = 0x0d800180 | hifields = 4 | lofields = 5 |

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