Changes

Jump to navigation Jump to search
m
no edit summary
{{rld|0x0d800058|32|HW_DBGINTSTS}}
{{rld|0x0d80005c|32|HW_DBGINTEN}}
{{rla|0x0d800060|32|HW_MEMIRRHW_SRNPROT|Memory Probably bus control / ; includes the SRAM bank swap ("HW_SRNPROT"){{check}}}}
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}}
{{rla|0x0d800070|32|HW_EXICTRLHW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other ("HW_AIP_PROT") {{check}}; probably related to Flipper interface compatibility}}{{rldrla|0x0d800074|32|HW_AIP_IOCTRLHW_AIPIOCTRL|??Probably related to Flipper interface compatibility/bus control}}
{{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}}
{{rld|0x0d800084|32|HW_USBDBG1}}
{{rld|0x0d800088|32|HW_USBFRCRST}}
{{rld|0x0d80008c|32|HW_USBIOTEST}}
{{rld|0x0d800090|32|HW_ELA_REG_ADDR|Unknown (perhaps test/debug"embedded logic-relatedanalyzer?!")|drs=4}}
{{rld|0x0d800094|32|HW_ELA_REG_DATA}}
{{rld|0x0d800098|32|HW_MEMTSTN}}
{{rld|0x0d8000f8|32|HW_GPIO_STRAPS}}
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers?|drs=18}}
{{rld|0x0d800104|32|HW_ARB_CFG_M1}}
{{rld|0x0d800108|32|HW_ARB_CFG_M2}}
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
{{rla|0x0d800180|32|HW_DIFLAGSHW_COMPAT|Some DI stuff and boot code and {{check}}}}{{rlarld|0x0d800184|32|HW_UNKFLAGSHW_RESET_AHB|{{check}}}}
{{rld|0x0d800188|32|HW_SPARE0|?}}
{{rla|0x0d80018c|32|HW_BOOT0|(HW_SPARE1ACR_SPARE1) Controls boot0 mapping? {{check}}}}
{{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}}
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
{{rld|0x0d80019c|32|HW_PLLDR|ClockingPLL/Clock configuration (?)|drs=12}}{{rla|0x0d8001b0|32|HW_PLLSYS|?}}{{rla|0x0d8001b4|32|HW_PLLSYSEXT|Clocking?}}{{rld|0x0d8001b8|32|HW_PLLDSK|Other clocking registers|drs=9?}}
{{rld|0x0d8001bc|32|HW_PLLDDR}}
{{rld|0x0d8001c0|32|HW_PLLDDREXT}}
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|HW_OTPDATA}}
{{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers (vestigial?)|drs=4}}
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
}}
{{reg32 | HW_MEMIRR HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 |
|16 |
|? |
| |H |SM |U4 |U3 |C |B |A ||
}}
This register controls seems to control visibility of various memory mappings? Bits devices or features. The value of the register during normal operation seems to depend on Hollywood revision.  * In boot1c, set to 0x47 if HWVER (in HW_VERSION) is 0 - otherwise, set to 0x7.* When BC is booting, set to 0x67 if HWVER is 0 - otherwise set to 0x27  It seems like bits 31-7 cannot be read or written to?{{check}}
{{regdesc
|H|Set [by boot1, BC, others] if VERHI HWVER in HW_VERSION is 0
|SM|Enables the SRAM mirror at 0xfffe0000 when set
|U4|Unknown
}}
{{reg32 | HW_EXICTRL HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 |
|16 |
|? |
|11|1 |3|1 |
|? |R/W|?|R/W |
| |DI | |EXI ENAHBIOPI ||
}}
This register controls at least the current EXI status. It's probably related to bus control/GC compatibility.
{{regdesc
|DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}}
|EXIENAHBIOPI|enable "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI.
}}
{{reg32 | HW_DIFLAGS HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 ||16 ||? || |||15|1 ||? |? || |ENAHBIOMEM ||}}This register is probably related to bus control/GC compatibility.{{regdesc|ENAHBIOMEM| This bit is named in IOSv3.}}  {{reg32 | HW_COMPAT| addr = 0x0d800180 | hifields = 4 | lofields = 4 5 ||10|1 |1 |4 ||? |R/W |R/W |? || |DVDVIDEO|PPCBOOT| |||13 11 |1 |2 |1 |1||? |? |R/W? |R/W|?|| |B4|? |? B1 | ||
}}
This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}}
|DVDVIDEO|Disables{{check}} DVD video support when set
|PPCBOOT|needs to be set to allow the PowerPC to read the boot stub.
|Bit 3 B4| unknownPotentially related to the IOSTRCTRL registers?|Bit 2 B1| when clear, disables bit 14 in the PPC IRQ flags
}}
|8|4 |4 |
|U|R |R |
| |VERHIHWVER|VERLOHWREV|
}}
This register contains the hardware revision of the Hollywood chipset. Observed values:
{{regdesc
|VERHIHWVER|Hollywood Version|VERLOHWREV|Hollywood Revision
}}
{{hwstub}}

Navigation menu