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| {{rld|0x0d800058|32|HW_DBGINTSTS}} | | {{rld|0x0d800058|32|HW_DBGINTSTS}} |
| {{rld|0x0d80005c|32|HW_DBGINTEN}} | | {{rld|0x0d80005c|32|HW_DBGINTEN}} |
− | {{rla|0x0d800060|32|HW_MEMIRR|Memory control / SRAM bank swap ("HW_SRNPROT"){{check}}}} | + | {{rla|0x0d800060|32|HW_SRNPROT|Probably bus control; includes the SRAM bank swap }} |
| {{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}} | | {{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB ("HW_BUSPROT")}} |
− | {{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other ("HW_AIP_PROT") {{check}}}} | + | {{rla|0x0d800070|32|HW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other; probably related to Flipper interface compatibility}} |
− | {{rld|0x0d800074|32|HW_AIP_IOCTRL|??}} | + | {{rla|0x0d800074|32|HW_AIPIOCTRL|Probably related to Flipper interface compatibility/bus control}} |
| {{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}} | | {{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}} |
| {{rld|0x0d800084|32|HW_USBDBG1}} | | {{rld|0x0d800084|32|HW_USBDBG1}} |
| {{rld|0x0d800088|32|HW_USBFRCRST}} | | {{rld|0x0d800088|32|HW_USBFRCRST}} |
| {{rld|0x0d80008c|32|HW_USBIOTEST}} | | {{rld|0x0d80008c|32|HW_USBIOTEST}} |
− | {{rld|0x0d800090|32|HW_ELA_REG_ADDR|Unknown (perhaps test/debug-related?)|drs=4}} | + | {{rld|0x0d800090|32|HW_ELA_REG_ADDR|Unknown ("embedded logic-analyzer?!")|drs=4}} |
| {{rld|0x0d800094|32|HW_ELA_REG_DATA}} | | {{rld|0x0d800094|32|HW_ELA_REG_DATA}} |
| {{rld|0x0d800098|32|HW_MEMTSTN}} | | {{rld|0x0d800098|32|HW_MEMTSTN}} |
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Line 63: |
| {{rld|0x0d8000f8|32|HW_GPIO_STRAPS}} | | {{rld|0x0d8000f8|32|HW_GPIO_STRAPS}} |
| {{rld|0x0d8000fc|32|HW_GPIO_OWNER}} | | {{rld|0x0d8000fc|32|HW_GPIO_OWNER}} |
− | {{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers|drs=18}} | + | {{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers?|drs=18}} |
| {{rld|0x0d800104|32|HW_ARB_CFG_M1}} | | {{rld|0x0d800104|32|HW_ARB_CFG_M1}} |
| {{rld|0x0d800108|32|HW_ARB_CFG_M2}} | | {{rld|0x0d800108|32|HW_ARB_CFG_M2}} |
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Line 81: |
| {{rld|0x0d800148|32|HW_ARB_PCNTCFG}} | | {{rld|0x0d800148|32|HW_ARB_PCNTCFG}} |
| {{rld|0x0d80014c|32|HW_ARB_PCNTSTS}} | | {{rld|0x0d80014c|32|HW_ARB_PCNTSTS}} |
− | {{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}} | + | {{rla|0x0d800180|32|HW_COMPAT| Some DI stuff and boot code and {{check}}}} |
− | {{rla|0x0d800184|32|HW_UNKFLAGS|{{check}}}} | + | {{rld|0x0d800184|32|HW_RESET_AHB|}} |
| {{rld|0x0d800188|32|HW_SPARE0|?}} | | {{rld|0x0d800188|32|HW_SPARE0|?}} |
− | {{rla|0x0d80018c|32|HW_BOOT0|(HW_SPARE1) Controls boot0 mapping? {{check}}}} | + | {{rla|0x0d80018c|32|HW_BOOT0|(ACR_SPARE1) Controls boot0 mapping? {{check}}}} |
| {{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}} | | {{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}} |
| {{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}} | | {{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}} |
| {{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}} | | {{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}} |
− | {{rld|0x0d80019c|32|HW_PLLDR|Clocking?}} | + | {{rld|0x0d80019c|32|HW_PLLDR|PLL/Clock configuration (?)|drs=12}} |
− | {{rla|0x0d8001b0|32|HW_PLLSYS|?}} | + | {{rla|0x0d8001b0|32|HW_PLLSYS}} |
− | {{rla|0x0d8001b4|32|HW_PLLSYSEXT|Clocking?}} | + | {{rla|0x0d8001b4|32|HW_PLLSYSEXT}} |
− | {{rld|0x0d8001b8|32|HW_PLLDSK|Other clocking registers|drs=9?}} | + | {{rld|0x0d8001b8|32|HW_PLLDSK}} |
| {{rld|0x0d8001bc|32|HW_PLLDDR}} | | {{rld|0x0d8001bc|32|HW_PLLDDR}} |
| {{rld|0x0d8001c0|32|HW_PLLDDREXT}} | | {{rld|0x0d8001c0|32|HW_PLLDDREXT}} |
Line 106: |
Line 106: |
| {{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}} | | {{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}} |
| {{rld|0x0d8001f0|32|HW_OTPDATA}} | | {{rld|0x0d8001f0|32|HW_OTPDATA}} |
− | {{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers (vestigial?)|drs=4}} | + | {{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers|drs=4}} |
| {{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}} | | {{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}} |
| {{rld|0x0d8001fc|32|HW_OBSCLKICTRL}} | | {{rld|0x0d8001fc|32|HW_OBSCLKICTRL}} |
Line 154: |
Line 154: |
| }} | | }} |
| | | |
− | {{reg32 | HW_MEMIRR | addr = 0x0d800060 | hifields = 1 | lofields = 8 | | + | {{reg32 | HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 | |
| |16 | | | |16 | |
| |? | | | |? | |
Line 162: |
Line 162: |
| | |H |SM |U4 |U3 |C |B |A || | | | |H |SM |U4 |U3 |C |B |A || |
| }} | | }} |
− | This register controls seems to control various memory mappings? Bits 31-7 cannot be read or written to? | + | This register controls seems to control visibility of various devices or features. |
| + | The value of the register during normal operation seems to depend on Hollywood revision. |
| + | |
| + | * In boot1c, set to 0x47 if HWVER (in HW_VERSION) is 0 - otherwise, set to 0x7. |
| + | * When BC is booting, set to 0x67 if HWVER is 0 - otherwise set to 0x27 |
| + | |
| + | |
| + | It seems like bits 31-7 cannot be read or written to? {{check}} |
| {{regdesc | | {{regdesc |
− | |H|Set [by boot1, BC, others] if VERHI in HW_VERSION is 0 | + | |H|Set [by boot1, BC, others] if HWVER in HW_VERSION is 0 |
| |SM|Enables the SRAM mirror at 0xfffe0000 when set | | |SM|Enables the SRAM mirror at 0xfffe0000 when set |
| |U4|Unknown | | |U4|Unknown |
Line 173: |
Line 180: |
| }} | | }} |
| | | |
− | {{reg32 | HW_EXICTRL | addr = 0x0d800070 | hifields = 1 | lofields = 4 | | + | {{reg32 | HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 | |
| |16 | | | |16 | |
| |? | | | |? | |
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| |11|1 |3|1 | | | |11|1 |3|1 | |
| |? |R/W|?|R/W | | | |? |R/W|?|R/W | |
− | | |DI | |EXI || | + | | |DI | |ENAHBIOPI || |
| }} | | }} |
− | This register controls at least the current EXI status. | + | This register controls at least the current EXI status. It's probably related to bus control/GC compatibility. |
| {{regdesc | | {{regdesc |
| |DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}} | | |DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}} |
− | |EXI|enable EXI bus | + | |ENAHBIOPI| "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI. |
| }} | | }} |
| | | |
− | {{reg32 | HW_DIFLAGS | addr = 0x0d800180 | hifields = 4 | lofields = 4 | | + | {{reg32 | HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 | |
− | |10|1 |1 |4 | | + | |16 | |
− | |? |R/W |R/W |? | | + | |? | |
− | | |DVDVIDEO|PPCBOOT| || | + | | || |
− | |13 |1 |1 |1| | + | |15|1 | |
− | |? |R/W|R/W|?| | + | |? |? | |
− | | |? |? | || | + | | |ENAHBIOMEM || |
| + | }} |
| + | This register is probably related to bus control/GC compatibility. |
| + | {{regdesc |
| + | |ENAHBIOMEM| This bit is named in IOSv3. |
| + | }} |
| + | |
| + | |
| + | {{reg32 | HW_COMPAT| addr = 0x0d800180 | hifields = 4 | lofields = 5 | |
| + | |10|1 |1 |4 | |
| + | |? |R/W |R/W |? | |
| + | | |DVDVIDEO|PPCBOOT| || |
| + | |11 |1 |2 |1 |1| |
| + | |? |? |? |R/W |?| |
| + | | |B4| |B1 | || |
| }} | | }} |
| This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}} | | This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}} |
Line 199: |
Line 220: |
| |DVDVIDEO|Disables{{check}} DVD video support when set | | |DVDVIDEO|Disables{{check}} DVD video support when set |
| |PPCBOOT|needs to be set to allow the PowerPC to read the boot stub. | | |PPCBOOT|needs to be set to allow the PowerPC to read the boot stub. |
− | |Bit 3 | unknown | + | |B4| Potentially related to the IOSTRCTRL registers? |
− | |Bit 2 | when clear, disables bit 14 in the PPC IRQ flags | + | |B1| when clear, disables bit 14 in the PPC IRQ flags |
| }} | | }} |
| | | |
Line 364: |
Line 385: |
| |8|4 |4 | | | |8|4 |4 | |
| |U|R |R | | | |U|R |R | |
− | | |VERHI|VERLO| | + | | |HWVER|HWREV| |
| }} | | }} |
− | This register contains the hardware revision of the Hollywood chipset. | + | This register contains the hardware revision of the Hollywood chipset. Observed values: |
| + | |
| + | * Hollywood ES1.x - 0x00 to 0x0f (?)<br> |
| + | * Hollywood ES2.0 - 0x10<br> |
| + | * Hollywood ES2.1 - 0x11 |
| + | |
| {{regdesc | | {{regdesc |
− | |VERHI|Version | + | |HWVER|Hollywood Version |
− | |VERLO|Revision | + | |HWREV|Hollywood Revision |
| }} | | }} |
| | | |
| | | |
| {{hwstub}} | | {{hwstub}} |