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add some entries/bits for clocking registers
{{rld|0x0d8001c0|32|HW_PLLDDREXT}}
{{rld|0x0d8001c4|32|HW_PLLVI}}
{{rldrla|0x0d8001c8|32|HW_PLLVIEXT}}
{{rld|0x0d8001cc|32|HW_PLLAI}}
{{rldrla|0x0d8001d0|32|HW_PLLAIEXT}}
{{rld|0x0d8001d4|32|HW_PLLUSB}}
{{rldrla|0x0d8001d8|32|HW_PLLUSBEXT}}
{{rld|0x0d8001dc|32|HW_IOPWRCTRL|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}
{{rld|0x0d8001e0|32|HW_IOSTRCTRL0|More clock registers?|drs=3}}
== General Registers ==
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
|16 |
|U |
| ||
|8|4 |4 |
|U|R |R |
| |VERHI|VERLO|
}}
This register contains the hardware revision of the Hollywood chipset.
{{regdesc
|VERHI|Version
|VERLO|Revision
}}
 
{{reg32 | HW_VIDIM | addr=0x0d80001c | hifields = 1 | lofields = 5 |
|16 |
|FX|Unknown, but IOS calls this "FX".
|SPEED|Sets the Hollywood clock to 243MHz when 0 (Wii mode) or 162MHz when 1 (GC mode)
}}
 
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
|5 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |
|U |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
| |NLCKB_EDRAM|RSTB_EDRAM|RSTB_AHB|RSTB_IOP|RSTB_DSP|RSTB_VI1|RSTB_VI|RSTB_IOPI|RSTB_IOMEM|RSTB_IODI|RSTB_IOEXI||
|1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |
|R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
|RSTB_IOSI|RSTB_AI_I2S3|RSTB_GFX|RSTB_GFXTCPE|RSTB_MEM|RSTB_DIRSTB|RSTB_PI|RSTB_MEMRSTB|NLCKB_SYSPLL|RSTB_SYSPLL|SRSTB_CPU|RSTB_CPU|RSTB_DSKPLL|RSTB_MEMRSTB|CRSTB|RSTBINB|
}}
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
{{regdesc
|NLCKB_EDRAM| Unlock external DRAM reset?
|RSTB_EDRAM| External DRAM reset
|RSTB_AHB| ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...
|RSTB_IOP| IOP/Starlet reset
|RSTB_VI1| VI1 reset?
|RSTB_VI| Video Interface reset
|RSTB_IOPI| [[Hardware/Processor_Interface|Processor Interface IO]] reset
|RSTB_IOMEM| [[Hardware/Memory_Interface|MEM IO]] reset
|RSTB_IODI| Disk Interface IO reset
|RSTB_IOEXI| EXI IO reset
|RSTB_IOSI| SI IO reset
|RSTB_AI_I2S3| Audio interface I2S3 reset
|RSTB_GFX| GFX reset?
|RSTB_GFXTCPE| GFX TCPE?
|RSTB_MEM| [[Hardware/Memory_Interface|MEM]] reset. If cleared, kills EXI-based starlet experimental proxy.
|RSTB_DIRSTB| Disk Interface reset B
}}
 
 
{{regdesc
|NLCKB_SYSPLL| Unlock SYSPLL reset?
|RSTB_SYSPLL| SYSPLL reset. If cleared, kills EXI-based starlet experimental proxy.
|SRSTB_CPU| PowerPC SRESET (release first)
|RSTB_CPU| PowerPC HRESET (release second)
|RSTB_DSKPLL| DSKPLL reset. Is cleared by IOS before modifying 1b8, and set again afterwards
|RSTB_MEMRSTB| MEM reset B. Also seems to reboot system.
|CRSTB| CRST? Also seems to reboot system.
|RSTBINB| System reset. Set to zero to reboot system.
}}
}}
{{reg32 | HW_RESETS HW_PLLVIEXT | addr = 0x0d800194 0x0d8001c8 | hifields = 12 3 | lofields = 16 1 ||5 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 14||U |R/W ? |R/W ?|R/W ? |R/W |R/W A |R/W B |R/W |R/W |R/W |R/W |R/W 16 || ? |NLCKB_EDRAM|RSTB_EDRAM |RSTB_AHB|RSTB_IOP}}Probably related to VI clocking.{{regdesc|RSTB_DSPA|RSTB_VI1|RSTB_VI|RSTB_IOPI|RSTB_IOMEM|RSTB_IODI|RSTB_IOEXIRelated to VI PLL initialization?|B|Related to VI PLL initialization?}}   {{reg32 |1 HW_PLLAIEXT |1 addr = 0x0d8001d0 |1 hifields = 3 |lofields = 1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 14||R/W ? |R/W ?|R/W ? |R/W |R/W A |R/W B |R/W |R/W |R/W |R/W 16 |R/W |R/W |R/W |R/W |R/W |R/W ? ||RSTB_IOSI|RSTB_AI_I2S3|RSTB_GFX|RSTB_GFXTCPE|RSTB_MEM|RSTB_DIRSTB|RSTB_PI|RSTB_MEMRSTB|NLCKB_SYSPLL|RSTB_SYSPLL|SRSTB_CPU|RSTB_CPU|RSTB_DSKPLL|RSTB_MEMRSTB|CRSTB |RSTBINB|
}}
This register seems Probably related to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1AI clocking.
{{regdesc
|NLCKB_EDRAMA| Unlock external DRAM resetRelated to AI PLL initialization?|RSTB_EDRAM| External DRAM resetB|RSTB_AHB| ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...|RSTB_IOP| IOP/Starlet reset|RSTB_VI1| VI1 resetRelated to AI PLL initialization?|RSTB_VI| Video Interface reset|RSTB_IOPI| [[Hardware/Processor_Interface|Processor Interface IO]] reset|RSTB_IOMEM| [[Hardware/Memory_Interface|MEM IO]] reset|RSTB_IODI| Disk Interface IO reset|RSTB_IOEXI| EXI IO reset|RSTB_IOSI| SI IO reset|RSTB_AI_I2S3| Audio interface I2S3 reset|RSTB_GFX| GFX reset?|RSTB_GFXTCPE| GFX TCPE?|RSTB_MEM| [[Hardware/Memory_Interface|MEM]] reset. If cleared, kills EXI-based starlet experimental proxy.|RSTB_DIRSTB| Disk Interface reset B
}}
{{reg32 | HW_PLLUSBEXT | addr = 0x0d8001d8 | hifields = 3 | lofields = 1 |
|1 |1 | 14|
|R/W? |R/W?| ? |
|A |B | ||
|16 |
|? |
| ||
}}
Probably related to USB clocking.
{{regdesc
|NLCKB_SYSPLLA| Unlock SYSPLL resetRelated to USB PLL initialization?|RSTB_SYSPLLB|Related to USB PLL initialization?}} {{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 ||16 | SYSPLL reset. If cleared, kills EXI-based starlet experimental proxy.|SRSTB_CPUU | PowerPC SRESET (release first)|RSTB_CPU || PowerPC HRESET (release second)|RSTB_DSKPLL8|4 |4 ||U|R |R | DSKPLL reset. Is cleared by IOS before modifying 1b8, and set again afterwards|RSTB_MEMRSTB| MEM reset B. Also seems to reboot systemVERHI|VERLO|}}This register contains the hardware revision of the Hollywood chipset.{{regdesc|CRSTBVERHI| CRST? Also seems to reboot system.Version|RSTBINBVERLO| System reset. Set to zero to reboot system.Revision
}}
 
 
{{hwstub}}

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