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}}
{{reg32 | HW_ACRPLLSYS HW_PLLSYS | addr = 0x0d8001b0 | hifields = 3 | lofields = 1 |
|5 |9 |2|
|?|R/W?| ? |
}}
{{reg32 | HW_ACRPLLSYSEXT HW_PLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
|16 |
|? |
|7 |9 |
||R/W?|
||clk_1CPUCLK||
}}
This register is involved in some sort of clocking.
{{regdesc
|clk_1CPUCLK|Unknown, probably bus clock, but IOS calls this "clk_1". 100J calls this "CPUCLK". This is probably the bus speed. Bit 8 is probably wired to 0. never set? <br>
243Mhz - 0x10<br>
176Mhz - 0x16<br>
162Mhz - 0x18<br>
...149Mhz - 0x1a<br>138Mhz - 0x1c<br>129Mhz - 0x1e<br>121Mhz - 0x20<br>114Mhz - 0x22<br>
108Mhz - 0x24
}}

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