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{{rld|0x0d800058|32|HW_DBGINTSTS}}
{{rld|0x0d80005c|32|HW_DBGINTEN}}
{{rla|0x0d800060|32|HW_MEMIRRHW_SRNPROT|Memory Probably bus control / ; includes the SRAM bank swap{{check}}}}{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB("HW_BUSPROT")}}{{rla|0x0d800070|32|HW_EXICTRLHW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other ; probably related to Flipper interface compatibility}}{{check}}rla|0x0d800074|32|HW_AIPIOCTRL|Probably related to Flipper interface compatibility/bus control}}
{{rld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}}
{{rld|0x0d800084|32|HW_USBDBG1}}
{{rld|0x0d800088|32|HW_USBFRCRST}}
{{rld|0x0d80008c|32|HW_USBIOTEST}}
{{rld|0x0d800090|32|HW_ELA_REG_ADDR|Unknown ("embedded logic-analyzer?!")|drs=4}}
{{rld|0x0d800094|32|HW_ELA_REG_DATA}}
{{rld|0x0d800098|32|HW_MEMTSTN}}
{{rld|0x0d80009c|32|HW_MEMTSTP}}
{{rld|0x0d8000c0|32|HW_GPIOB_OUT|[[Hardware/Hollywood GPIOs|Hollywood GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|HW_GPIOB_DIR}}
{{rld|0x0d8000f8|32|HW_GPIO_STRAPS}}
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers?|drs=18}}
{{rld|0x0d800104|32|HW_ARB_CFG_M1}}
{{rld|0x0d800108|32|HW_ARB_CFG_M2}}
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
{{rla|0x0d800180|32|HW_DIFLAGSHW_COMPAT|Some DI stuff and boot code and {{check}}}}{{rlarld|0x0d800184|32|HW_UNKFLAGSHW_RESET_AHB|}}{{check}}rld|0x0d800188|32|HW_SPARE0|?}}{{rla|0x0d80018c|32|HW_BOOT0|Maps (ACR_SPARE1) Controls boot0 mapping? {{check}}}}
{{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}}
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
{{rld|0x0d80019c|32|HW_PLLDR|PLL/Clock configuration (?)|drs=12}}{{rla|0x0d8001b0|32|HW_PLLSYS|?}}{{rla|0x0d8001b4|32|HW_PLLSYSEXT}}{{rld|0x0d8001b8|32|HW_PLLDSK}}{{rld|0x0d8001bc|32|HW_PLLDDR}}{{rld|0x0d8001c0|32|HW_PLLDDREXT}}{{rld|0x0d8001c4|32|HW_PLLVI}}{{rla|0x0d8001c8|32|HW_PLLVIEXT}}{{rld|0x0d8001cc|32|HW_PLLAI}}{{rla|0x0d8001d0|32|HW_PLLAIEXT}}{{rld|0x0d8001d4|32|HW_PLLUSB}}{{rla|0x0d8001d8|32|Clocking?HW_PLLUSBEXT}}{{rld|0x0d8001dc|32|HW_SSPOWERHW_IOPWRCTRL|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}{{rld|0x0d8001e0|32|HW_IOSTRCTRL0|More clock registers?|drs=3}}{{rld|0x0d8001e4|32|HW_IOSTRCTRL1}}{{rld|0x0d8001e8|32|HW_CLKSTRCTRL}}
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|HW_OTPDATA}}
{{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers|drs=4}}
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
{{rld|0x0d800200|32|HW_DBGPORT}}
{{rld|0x0d800204|32|HW_SICLKDIV|SI-related, unused?|drs=4}}
{{rld|0x0d800208|32|HW_SICTRL}}
== General Registers ==
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
|16 |
|U |
| ||
|8|4 |4 |
|U|R |R |
| |VERHI|VERLO|
}}
This register contains the hardware revision of the Hollywood chipset.
{{regdesc
|VERHI|Version
|VERLO|Revision
}}
 
{{reg32 | HW_VIDIM | addr=0x0d80001c | hifields = 1 | lofields = 5 |
|16 |
}}
{{reg32 | HW_MEMIRR HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 |
|16 |
|? |
| |H |SM |U4 |U3 |C |B |A ||
}}
This register controls seems to control visibility of various memory mappings? Bits devices or features. The value of the register during normal operation seems to depend on Hollywood revision.  * In boot1c, set to 0x47 if HWVER (in HW_VERSION) is 0 - otherwise, set to 0x7.* When BC is booting, set to 0x67 if HWVER is 0 - otherwise set to 0x27  It seems like bits 31-7 cannot be read or written to?{{check}}
{{regdesc
|H|Set [by boot1, BC, others] if VERHI HWVER in HW_VERSION is 0
|SM|Enables the SRAM mirror at 0xfffe0000 when set
|U4|Unknown
}}
{{reg32 | HW_EXICTRL HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 |
|16 |
|? |
|11|1 |3|1 |
|? |R/W|?|R/W |
| |DI | |EXI ENAHBIOPI ||
}}
This register controls at least the current EXI status. It's probably related to bus control/GC compatibility.
{{regdesc
|DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}}
|ENAHBIOPI| "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI.}} {{reg32 | HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 ||16 ||enable EXI ? || |||15|1 ||? |? || |ENAHBIOMEM ||}}This register is probably related to buscontrol/GC compatibility.{{regdesc|ENAHBIOMEM| This bit is named in IOSv3.
}}
 {{reg32 | HW_DIFLAGS HW_COMPAT| addr = 0x0d800180 | hifields = 4 | lofields = 4 5 ||10|1 |1 |4 ||? |R/W |R/W |? || |DVDVIDEO|PPCBOOT| |||13 11 |1 |2 |1 |1||? |? |R/W? |R/W|?|| |B4|? |? B1 | ||
}}
This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}}
|DVDVIDEO|Disables{{check}} DVD video support when set
|PPCBOOT|needs to be set to allow the PowerPC to read the boot stub.
|Bit 3 B4| unknownPotentially related to the IOSTRCTRL registers?|Bit 2 B1| when clear, disables bit 14 in the PPC IRQ flags
}}
|FX|Unknown, but IOS calls this "FX".
|SPEED|Sets the Hollywood clock to 243MHz when 0 (Wii mode) or 162MHz when 1 (GC mode)
}}
 
{{reg32 | HW_ACRPLLSYS | addr = 0x0d8001b0 | hifields = 3 | lofields = 1 |
|5 |9 |2|
|?|R/W?| ? |
||clk_0|||
|16 |
|? |
| ||
}}
This register is involved in some sort of clocking.
{{regdesc
|clk_0|Unknown, but IOS calls this "clk_0".
}}
 
{{reg32 | HW_ACRPLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
|16 |
|? |
| ||
|7 |9 |
||R/W?|
||clk_1||
}}
This register is involved in some sort of clocking.
{{regdesc
|clk_1|Unknown, but IOS calls this "clk_1".
}}
|RSTBINB| System reset. Set to zero to reboot system.
}}
 
{{reg32 | HW_PLLSYS | addr = 0x0d8001b0 | hifields = 3 | lofields = 1 |
|5 |9 |2|
|?|R/W?| ? |
||clk_0|||
|16 |
|? |
| ||
}}
This register is involved in some sort of clocking.
{{regdesc
|clk_0|Unknown, but IOS calls this "clk_0".
}}
 
{{reg32 | HW_PLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
|16 |
|? |
| ||
|7 |9 |
||R/W?|
||CPUCLK||
}}
This register is involved in some sort of clocking.
{{regdesc
|CPUCLK|IOS calls this "clk_1". 100J calls this "CPUCLK". This is probably the bus speed. Bit 8 is never set? <br>
 
243Mhz - 0x10<br>
216Mhz - 0x12<br>
194Mhz - 0x14<br>
176Mhz - 0x16<br>
162Mhz - 0x18<br>
149Mhz - 0x1a<br>
138Mhz - 0x1c<br>
129Mhz - 0x1e<br>
121Mhz - 0x20<br>
114Mhz - 0x22<br>
108Mhz - 0x24
}}
 
{{reg32 | HW_PLLVIEXT | addr = 0x0d8001c8 | hifields = 3 | lofields = 1 |
|1 |1 | 14|
|R/W? |R/W?| ? |
|A |B | ||
|16 |
|? |
| ||
}}
Probably related to VI clocking.
{{regdesc
|A|Related to VI PLL initialization?
|B|Related to VI PLL initialization?
}}
 
 
 
{{reg32 | HW_PLLAIEXT | addr = 0x0d8001d0 | hifields = 3 | lofields = 1 |
|1 |1 | 14|
|R/W? |R/W?| ? |
|A |B | ||
|16 |
|? |
| ||
}}
Probably related to AI clocking.
{{regdesc
|A|Related to AI PLL initialization?
|B|Related to AI PLL initialization?
}}
 
 
{{reg32 | HW_PLLUSBEXT | addr = 0x0d8001d8 | hifields = 3 | lofields = 1 |
|1 |1 | 14|
|R/W? |R/W?| ? |
|A |B | ||
|16 |
|? |
| ||
}}
Probably related to USB clocking.
{{regdesc
|A|Related to USB PLL initialization?
|B|Related to USB PLL initialization?
}}
 
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
|16 |
|U |
| ||
|8|4 |4 |
|U|R |R |
| |HWVER|HWREV|
}}
This register contains the hardware revision of the Hollywood chipset. Observed values:
 
* Hollywood ES1.x - 0x00 to 0x0f (?)<br>
* Hollywood ES2.0 - 0x10<br>
* Hollywood ES2.1 - 0x11
 
{{regdesc
|HWVER|Hollywood Version
|HWREV|Hollywood Revision
}}
 
 
{{hwstub}}

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