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start adding previously undocumented registers (from acrdump on 100J/121J)
{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
{{rld|0x0d800014|32|HW_ALARM}}
{{rld|0x0d800018|32|HW_PPCSPEEDHW_VI1CFG|[[Hardware/PPC Speed Control|PPC Speed Control]]VI-configuration related, unused?}}
{{rla|0x0d80001C|32|HW_VIDIM|Dims the video output}}
{{rla|0x0d800024|32|HW_VISOLID|Sets the video output to a solid color}}
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
{{rld|0x0d800040|32|HW_ARMFIQMASK|Various (mostly unused?) interrupt registers|drs=8}}
{{rld|0x0d800044|32|HW_IOPINTPPC}}
{{rld|0x0d800048|32|HW_WDGINTSTS}}
{{rld|0x0d80004c|32|HW_WDGCFG}}
{{rld|0x0d800050|32|HW_DMAADRINTSTS}}
{{rld|0x0d800054|32|HW_CPUADRINTSTS}}
{{rld|0x0d800058|32|HW_DBGINTSTS}}
{{rld|0x0d80005c|32|HW_DBGINTEN}}
{{rla|0x0d800060|32|HW_MEMIRR|Memory control / SRAM bank swap{{check}}}}
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB}}
{{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
{{rld|0x0d8000740x0d800080|32|HW_DDRCTRL_ADDRHW_USBDBG0|[[Hardware/DDR Control|DDR Control]]USB-related, unused?|drs=24}}{{rld|0x0d800084|32|HW_USBDBG1}}{{rld|0x0d800088|32|HW_USBFRCRST}}{{rld|0x0d8000760x0d80008c|32|HW_DDRCTRL_VALHW_USBIOTEST}}
{{rld|0x0d8000c0|32|HW_GPIOB_OUT|[[Hardware/Hollywood GPIOs|Hollywood GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|HW_GPIOB_DIR}}
{{rld|0x0d8000d0|32|HW_GPIOB_INTFLAG}}
{{rld|0x0d8000d4|32|HW_GPIOB_INTMASK}}
{{rld|0x0d8000d8|32|HW_GPIOB_INMIRHW_GPIOB_STRAPS}}
{{rld|0x0d8000dc|32|HW_GPIO_ENABLE}}
{{rld|0x0d8000e0|32|HW_GPIO_OUT}}
{{rld|0x0d8000f0|32|HW_GPIO_INTFLAG}}
{{rld|0x0d8000f4|32|HW_GPIO_INTMASK}}
{{rld|0x0d8000f8|32|HW_GPIO_INMIRHW_GPIO_STRAPS}}
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers|drs=18}}
{{rld|0x0d800104|32|HW_ARB_CFG_M1}}
{{rld|0x0d800108|32|HW_ARB_CFG_M2}}
{{rld|0x0d80010c|32|HW_ARB_CFG_M3}}
{{rld|0x0d800110|32|HW_ARB_CFG_M4}}
{{rld|0x0d800114|32|HW_ARB_CFG_M5}}
{{rld|0x0d800118|32|HW_ARB_CFG_M6}}
{{rld|0x0d80011c|32|HW_ARB_CFG_M7}}
{{rld|0x0d800120|32|HW_ARB_CFG_M8}}
{{rld|0x0d800124|32|HW_ARB_CFG_M9}}
{{rld|0x0d800130|32|HW_ARB_CFG_MC}}
{{rld|0x0d800134|32|HW_ARB_CFG_MD}}
{{rld|0x0d800138|32|HW_ARB_CFG_ME}}
{{rld|0x0d80013c|32|HW_ARB_CFG_MF}}
{{rld|0x0d800140|32|HW_ARB_CFG_CPU}}
{{rld|0x0d800144|32|HW_ARB_CFG_DMA}}
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
{{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}}
{{rla|0x0d800184|32|HW_UNKFLAGS|{{check}}}}
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
{{rla|0x0d8001b0|32|HW_ACRPLLSYSHW_PLLSYS|?}}{{rla|0x0d8001b4|32|HW_ACRPLLSYSEXTHW_PLLSYSEXT|Clocking?}}
{{rld|0x0d8001dc|32|HW_SSPOWER|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|HW_OTPDATA}}
{{rld|0x0d800204|32|HW_SICLKDIV|SI-related, unused?|drs=4}}
{{rld|0x0d800208|32|HW_SICTRL}}
{{rld|0x0d80020c|32|HW_SIDATA}}
{{rld|0x0d800210|32|HW_SIINT}}
{{rla|0x0d800214|32|HW_VERSION|Hollywood version}}
{{rld|0x0d8b420a|16|MEM_PROT|MEM2 protection enable}}

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