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some info on MEMIRR bits
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
{{rldrla|0x0d800060|32|HW_MEMIRR|Memory control / SRAM bank swap{{check}}}}
{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB}}
{{rla|0x0d800070|32|HW_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
|Y|Luma component
|E|Turns solid colour on/off
}}
 
{{reg32 | HW_MEMIRR | addr = 0x0d800060 | hifields = 1 | lofields = 8 |
|16 |
|? |
| ||
|9 |1 |1 |1 |1 |1 |1 |1 |
|? |R/W|R/W|R/W|R/W|R/W|R/W|R/W|
| |H |SM |U4 |U3 |C |B |A ||
}}
This register controls seems to control various memory mappings? Bits 31-7 cannot be read or written to?
{{regdesc
|H|Set [by boot1, BC, others] if VERHI in HW_VERSION is 0
|SM|Enables the SRAM mirror at 0xfffe0000 when set
|U4|Unknown
|U3|Set/cleared by syscall 0x54 in IOS58; maybe related to HW_AHBPROT
|C|Explicitly set by boot0/boot1 before using NAND/AES/SHA
|B|Explicitly set by boot0/boot1 before using NAND/AES/SHA
|A|Explicitly set by boot0/boot1 before using NAND/AES/SHA
}}

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