Changes

Jump to navigation Jump to search
922 bytes added ,  03:29, 3 October 2019
From Wii U OSv9
Line 198: Line 198:     
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
 
{{reg32 | HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 |
|5                      |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |
+
|5                      |1         |1         |1       |1       |1       |1       |1     |1       |1         |1         |1       |
|U                      |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
+
|U                      |R/W       |R/W       |R/W     |R/W     |R/W     |R/W     |R/W   |R/W     |R/W       |R/W       |R/W     |
|                        |||HANG|||||DDR2||DI2 |DDR1||
+
|                        |NLCKB_EDRAM|RSTB_EDRAM|RSTB_AHB|RSTB_IOP|RSTB_DSP|RSTB_VI1|RSTB_VI|RSTB_IOPI|RSTB_IOMEM|RSTB_IODI|RSTB_IOEXI||
|1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |1   |
+
|1       |1           |1       |1           |1       |1         |1     |1           |1           |1         |1       |1       |1         |1           |1   |1     |
|R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |
+
|R/W     |R/W         |R/W     |R/W         |R/W     |R/W       |R/W   |R/W         |R/W         |R/W       |R/W     |R/W     |R/W       |R/W         |R/W |R/W   |
||||||DI  |||||SRST|HRST||SYS3|SYS2|SYS |
+
|RSTB_IOSI|RSTB_AI_I2S3|RSTB_GFX|RSTB_GFXTCPE|RSTB_MEM|RSTB_DIRSTB|RSTB_PI|RSTB_MEMRSTB|NLCKB_SYSPLL|RSTB_SYSPLL|SRSTB_CPU|RSTB_CPU|RSTB_DSKPLL|RSTB_MEMRSTB|CRSTB|RSTBINB|
 
}}
 
}}
 
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
 
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
 
{{regdesc
 
{{regdesc
|HANG|System reset without recovery? Kills DI, sets slot LED on, hangs starlet...
+
|NLCKB_EDRAM| Unlock external DRAM reset?
|DDR2|seems to be related to the GDDR3 memory
+
|RSTB_EDRAM| External DRAM reset
|DI2|DI reset 2?
+
|RSTB_AHB| ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...
|DDR1|seems to be related to the GDDR3 memory
+
|RSTB_IOP| IOP/Starlet reset
|P|If cleared, kills EXI-based starlet experimental proxy.
+
|RSTB_VI1| VI1 reset?
|DI|DI reset
+
|RSTB_VI| Video Interface reset
|U|If cleared, kills EXI-based starlet experimental proxy.
+
|RSTB_IOPI| [[Processor_Interface|Processor Interface IO]] reset
|V|Is cleared by IOS before modifying 1b8, and set again afterwards
+
|RSTB_IOMEM| [[Memory_Interface||MEM IO]] reset
|SRST|PowerPC SRESET (release first)
+
|RSTB_IODI| Disk Interface IO reset
|HRST|PowerPC HRESET (release second)
+
|RSTB_IOEXI| EXI IO reset
|SYS3|System reset 3. Also seems to reboot system.
+
|RSTB_IOSI| SI IO reset
|SYS2|System reset 2. Also seems to reboot system.
+
|RSTB_AI_I2S3| Audio interface I2S3 reset
|SYS|System reset. Set to zero to reboot system.
+
|RSTB_GFX| GFX reset?
 +
|RSTB_GFXTCPE| GFX TCPE?
 +
|RSTB_MEM| [[Memory_Interface|MEM]] reset. If cleared, kills EXI-based starlet experimental proxy.
 +
|RSTB_DIRSTB| Disk Interface reset B
 +
|NLCKB_SYSPLL| Unlock SYSPLL reset?
 +
|RSTB_SYSPLL| SYSPLL reset. If cleared, kills EXI-based starlet experimental proxy.
 +
|SRSTB_CPU| PowerPC SRESET (release first)
 +
|RSTB_CPU| PowerPC HRESET (release second)
 +
|RSTB_DSKPLL| DSKPLL reset. Is cleared by IOS before modifying 1b8, and set again afterwards
 +
|RSTB_MEMRSTB| MEM reset B. Also seems to reboot system.
 +
|CRSTB| CRST? Also seems to reboot system.
 +
|RSTBINB| System reset. Set to zero to reboot system.
 
}}
 
}}
 
{{hwstub}}
 
{{hwstub}}

Navigation menu