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{{rld|0x0d800010|32|HW_TIMER|[[Hardware/Starlet Timer|Starlet Timer]]|drs=2}}
{{rld|0x0d800014|32|HW_ALARM}}
{{rld|0x0d800018|32|HW_PPCSPEEDHW_VI1CFG|[[Hardware/PPC Speed Control|PPC Speed Control]]VI-configuration related, unused?}}
{{rla|0x0d80001C|32|HW_VIDIM|Dims the video output}}
{{rla|0x0d800024|32|HW_VISOLID|Sets the video output to a solid color}}
{{rld|0x0d800030|32|HW_PPCIRQFLAG|[[Hardware/Hollywood IRQs|Hollywood IRQ controller]]|drs=412}}
{{rld|0x0d800034|32|HW_PPCIRQMASK}}
{{rld|0x0d800038|32|HW_ARMIRQFLAG}}
{{rld|0x0d80003c|32|HW_ARMIRQMASK}}
{{rld|0x0d800040|32|HW_ARMFIQMASK}}{{rld|0x0d800044|32|HW_IOPINTPPC}}{{rld|0x0d800048|32|HW_WDGINTSTS}}{{rld|0x0d80004c|32|HW_WDGCFG}}{{rld|0x0d800050|32|HW_DMAADRINTSTS}}{{rld|0x0d800054|32|HW_CPUADRINTSTS}}{{rld|0x0d800058|32|HW_DBGINTSTS}}{{rld|0x0d80005c|32|HW_DBGINTEN}}{{rla|0x0d800060|32|HW_MEMIRRHW_SRNPROT|Memory Probably bus control / ; includes the SRAM bank swap{{check}}}}{{rld|0x0d800064|32|HW_AHBPROT|Access control for the PPC to access devices on the AHB("HW_BUSPROT")}}{{rla|0x0d800070|32|HW_EXICTRLHW_AIPPROT|[[Hardware/EXI|EXI]] PPC enable / control / other ; probably related to Flipper interface compatibility}}{{rla|0x0d800074|32|HW_AIPIOCTRL|Probably related to Flipper interface compatibility/bus control}}{{checkrld|0x0d800080|32|HW_USBDBG0|USB-related, unused?|drs=4}}{{rld|0x0d800084|32|HW_USBDBG1}}{{rld|0x0d800088|32|HW_USBFRCRST}}{{rld|0x0d8000740x0d80008c|32|HW_DDRCTRL_ADDRHW_USBIOTEST}}{{rld|0x0d800090|32|[[Hardware/DDR ControlHW_ELA_REG_ADDR|DDR Control]]Unknown ("embedded logic-analyzer?!")|drs=24}}{{rld|0x0d800094|32|HW_ELA_REG_DATA}}{{rld|0x0d800098|32|HW_MEMTSTN}}{{rld|0x0d8000760x0d80009c|32|HW_DDRCTRL_VALHW_MEMTSTP}}
{{rld|0x0d8000c0|32|HW_GPIOB_OUT|[[Hardware/Hollywood GPIOs|Hollywood GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|HW_GPIOB_DIR}}
{{rld|0x0d8000d0|32|HW_GPIOB_INTFLAG}}
{{rld|0x0d8000d4|32|HW_GPIOB_INTMASK}}
{{rld|0x0d8000d8|32|HW_GPIOB_INMIRHW_GPIOB_STRAPS}}
{{rld|0x0d8000dc|32|HW_GPIO_ENABLE}}
{{rld|0x0d8000e0|32|HW_GPIO_OUT}}
{{rld|0x0d8000f0|32|HW_GPIO_INTFLAG}}
{{rld|0x0d8000f4|32|HW_GPIO_INTMASK}}
{{rld|0x0d8000f8|32|HW_GPIO_INMIRHW_GPIO_STRAPS}}
{{rld|0x0d8000fc|32|HW_GPIO_OWNER}}
{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB-related registers?|drs=18}}{{rld|0x0d800104|32|HW_ARB_CFG_M1}}{{rld|0x0d800108|32|HW_ARB_CFG_M2}}{{rld|0x0d80010c|32|HW_ARB_CFG_M3}}{{rld|0x0d800110|32|HW_ARB_CFG_M4}}{{rld|0x0d800114|32|HW_ARB_CFG_M5}}{{rld|0x0d800118|32|HW_ARB_CFG_M6}}{{rld|0x0d80011c|32|HW_ARB_CFG_M7}}{{rld|0x0d800120|32|HW_ARB_CFG_M8}}{{rld|0x0d800124|32|HW_ARB_CFG_M9}}{{rld|0x0d800130|32|HW_ARB_CFG_MC}}{{rld|0x0d800134|32|HW_ARB_CFG_MD}}{{rld|0x0d800138|32|HW_ARB_CFG_ME}}{{rld|0x0d80013c|32|HW_ARB_CFG_MF}}{{rld|0x0d800140|32|HW_ARB_CFG_CPU}}{{rld|0x0d800144|32|HW_ARB_CFG_DMA}}{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}{{rla|0x0d800180|32|HW_DIFLAGSHW_COMPAT|Some DI stuff and boot code and {{check}}}}{{rlarld|0x0d800184|32|HW_UNKFLAGSHW_RESET_AHB|}}{{check}}rld|0x0d800188|32|HW_SPARE0|?}}{{rla|0x0d80018c|32|HW_BOOT0|Maps (ACR_SPARE1) Controls boot0 mapping? {{check}}}}
{{rla|0x0d800190|32|HW_CLOCKS|clock stuff?}}
{{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|HW_IFPOWER|set to 0xFFFFFF when Wii wakes up ("interfaces")}}
{{rld|0x0d80019c|32|HW_PLLDR|PLL/Clock configuration (?)|drs=12}}{{rla|0x0d8001b0|32|HW_ACRPLLSYSHW_PLLSYS}}{{rla|0x0d8001b4|32|HW_PLLSYSEXT}}{{rld|0x0d8001b8|32|HW_PLLDSK}}{{rld|0x0d8001bc|32|HW_PLLDDR}}{{rld|0x0d8001c0|32|HW_PLLDDREXT}}{{rld|0x0d8001c4|32|HW_PLLVI}}{{rla|0x0d8001c8|32|HW_PLLVIEXT}}{{rld|0x0d8001cc|?32|HW_PLLAI}}{{rla|0x0d8001b40x0d8001d0|32|HW_PLLAIEXT}}{{rld|0x0d8001d4|32|HW_ACRPLLSYSEXTHW_PLLUSB}}{{rla|0x0d8001d8|32|Clocking?HW_PLLUSBEXT}}{{rld|0x0d8001dc|32|HW_SSPOWERHW_IOPWRCTRL|set to 0xFFFFFFF when Wii wakes up ("subsystems")}}{{rld|0x0d8001e0|32|HW_IOSTRCTRL0|More clock registers?|drs=3}}{{rld|0x0d8001e4|32|HW_IOSTRCTRL1}}{{rld|0x0d8001e8|32|HW_CLKSTRCTRL}}
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|HW_OTPDATA}}
{{rld|0x0d8001f4|32|HW_DBGCLK|Debug registers|drs=4}}
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
{{rld|0x0d800200|32|HW_DBGPORT}}
{{rld|0x0d800204|32|HW_SICLKDIV|SI-related, unused?|drs=4}}
{{rld|0x0d800208|32|HW_SICTRL}}
{{rld|0x0d80020c|32|HW_SIDATA}}
{{rld|0x0d800210|32|HW_SIINT}}
{{rla|0x0d800214|32|HW_VERSION|Hollywood version}}
{{rld|0x0d8b420a|16|MEM_PROT|MEM2 protection enable}}
== General Registers ==
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
|16 |
|U |
| ||
|8|4 |4 |
|U|R |R |
| |VERHI|VERLO|
}}
This register contains the hardware revision of the Hollywood chipset.
{{regdesc
|VERHI|Version
|VERLO|Revision
}}
 
{{reg32 | HW_VIDIM | addr=0x0d80001c | hifields = 1 | lofields = 5 |
|16 |
}}
{{reg32 | HW_EXICTRL HW_SRNPROT | addr = 0x0d800060 | hifields = 1 | lofields = 8 ||16 ||? || |||9 |1 |1 |1 |1 |1 |1 |1 ||? |R/W|R/W|R/W|R/W|R/W|R/W|R/W|| |H |SM |U4 |U3 |C |B |A ||}}This register controls seems to control visibility of various devices or features. The value of the register during normal operation seems to depend on Hollywood revision.  * In boot1c, set to 0x47 if HWVER (in HW_VERSION) is 0 - otherwise, set to 0x7.* When BC is booting, set to 0x67 if HWVER is 0 - otherwise set to 0x27  It seems like bits 31-7 cannot be read or written to? {{check}}{{regdesc|H|Set [by boot1, BC, others] if HWVER in HW_VERSION is 0|SM|Enables the SRAM mirror at 0xfffe0000 when set|U4|Unknown|U3|Set/cleared by syscall 0x54 in IOS58; maybe related to HW_AHBPROT|C|Explicitly set by boot0/boot1 before using NAND/AES/SHA|B|Explicitly set by boot0/boot1 before using NAND/AES/SHA|A|Explicitly set by boot0/boot1 before using NAND/AES/SHA}} {{reg32 | HW_AIPPROT | addr = 0x0d800070 | hifields = 1 | lofields = 4 ||16 ||? || |||11|1 |3|1 ||? |R/W|?|R/W || |DI | |ENAHBIOPI ||}}This register controls at least the current EXI status. It's probably related to bus control/GC compatibility.{{regdesc|DI|unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared{{check}}|ENAHBIOPI| "Enables the EXI bus." This bit is named in IOSv3. It's likely this is related to more than EXI.}} {{reg32 | HW_AIPIOCTRL | addr = 0x0d800074 | hifields = 1 | lofields = 2 |
|16 |
|? |
| ||
|15|1 |
|? |R/W ? || |EXI ENAHBIOMEM ||
}}
This register controls at least the current EXI statusis probably related to bus control/GC compatibility.
{{regdesc
|EXIENAHBIOMEM|enable EXI busThis bit is named in IOSv3.
}}
 {{reg32 | HW_DIFLAGS HW_COMPAT| addr = 0x0d800180 | hifields = 3 4 | lofields = 1 5 ||11 10|1 |1 |4 ||? |R/W |R/W |? || |DVDVIDEO|PPCBOOT| |||16 11 |1 |2 |1 |1||? |? |? |R/W |?|| |B4| |B1 | ||
}}
This register seems to control some aspects of the PowerPC booting and some DI flags.{{check}}
{{regdesc
|DVDVIDEO|Disables{{check}} DVD video support when set
|PPCBOOT|needs to be set to allow the PowerPC to read the boot stub.
|Bit 2 B4| Potentially related to the IOSTRCTRL registers?|B1| when clear, disables bit 14 in the PPC IRQ flags
}}
{{reg32 | HW_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 9 |
|16 |
|? |
| ||
|1|2 |1 |1 |1 |6 |1 |2 |12 1 ||?|R/W |R/W |R/W|R/W | ? |R/W|? |R/W|| |DSKPLLSRC|BOOT0| B11 |B10| |A3 | |A0 ||
}}
This register at least controls the boot0 memory mapping and DSK PLL source.
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
|B11|Explicitly set by the [IOS58] kernel on boot
|B10|Explicitly set by the [IOS58] kernel on boot
|A3|AHB-related? - polled on AHB flush? Related to bit 16 in 0x0d800188?
|A0|AHB-related? - polled on AHB flush? Related to bit 16 in 0x0d800188?
}}
}}
{{reg32 | HW_ACRPLLSYS HW_RESETS | addr = 0x0d800194 | hifields = 12 | lofields = 16 ||5 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 ||U |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W || |NLCKB_EDRAM|RSTB_EDRAM|RSTB_AHB|RSTB_IOP|RSTB_DSP|RSTB_VI1|RSTB_VI|RSTB_IOPI|RSTB_IOMEM|RSTB_IODI|RSTB_IOEXI|||1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 |1 ||R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W |R/W ||RSTB_IOSI|RSTB_AI_I2S3|RSTB_GFX|RSTB_GFXTCPE|RSTB_MEM|RSTB_DIRSTB|RSTB_PI|RSTB_MEMRSTB|NLCKB_SYSPLL|RSTB_SYSPLL|SRSTB_CPU|RSTB_CPU|RSTB_DSKPLL|RSTB_MEMRSTB|CRSTB|RSTBINB|}}This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.{{regdesc|NLCKB_EDRAM| Unlock external DRAM reset?|RSTB_EDRAM| External DRAM reset|RSTB_AHB| ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...|RSTB_IOP| IOP/Starlet reset|RSTB_VI1| VI1 reset?|RSTB_VI| Video Interface reset|RSTB_IOPI| [[Hardware/Processor_Interface|Processor Interface IO]] reset|RSTB_IOMEM| [[Hardware/Memory_Interface|MEM IO]] reset|RSTB_IODI| Disk Interface IO reset|RSTB_IOEXI| EXI IO reset|RSTB_IOSI| SI IO reset|RSTB_AI_I2S3| Audio interface I2S3 reset|RSTB_GFX| GFX reset?|RSTB_GFXTCPE| GFX TCPE?|RSTB_MEM| [[Hardware/Memory_Interface|MEM]] reset. If cleared, kills EXI-based starlet experimental proxy.|RSTB_DIRSTB| Disk Interface reset B}}  {{regdesc|NLCKB_SYSPLL| Unlock SYSPLL reset?|RSTB_SYSPLL| SYSPLL reset. If cleared, kills EXI-based starlet experimental proxy.|SRSTB_CPU| PowerPC SRESET (release first)|RSTB_CPU| PowerPC HRESET (release second)|RSTB_DSKPLL| DSKPLL reset. Is cleared by IOS before modifying 1b8, and set again afterwards|RSTB_MEMRSTB| MEM reset B. Also seems to reboot system.|CRSTB| CRST? Also seems to reboot system.|RSTBINB| System reset. Set to zero to reboot system.}} {{reg32 | HW_PLLSYS | addr = 0x0d8001b0 | hifields = 3 | lofields = 1 |
|5 |9 |2|
|?|R/W?| ? |
}}
{{reg32 | HW_ACRPLLSYSEXT HW_PLLSYSEXT | addr = 0x0d8001b4 | hifields = 1 | lofields = 2 |
|16 |
|? |
|7 |9 |
||R/W?|
||clk_1CPUCLK||
}}
This register is involved in some sort of clocking.
{{regdesc
|clk_1CPUCLK|Unknown, but IOS calls this "clk_1".100J calls this "CPUCLK". This is probably the bus speed. Bit 8 is never set? <br> 243Mhz - 0x10<br>216Mhz - 0x12<br>194Mhz - 0x14<br>176Mhz - 0x16<br>162Mhz - 0x18<br>149Mhz - 0x1a<br>138Mhz - 0x1c<br>129Mhz - 0x1e<br>121Mhz - 0x20<br>114Mhz - 0x22<br>108Mhz - 0x24
}}
{{reg32 | HW_RESETS HW_PLLVIEXT | addr = 0x0d800194 0x0d8001c8 | hifields = 12 3 | lofields = 16 1 ||5 1 |1 |1 14||R/W? |R/W?| ? ||A |B |1 |||16 ||1 ? |1 |1 |1 |1 }}Probably related to VI clocking.{{regdesc|1 A|1 Related to VI PLL initialization?|1 B|Related to VI PLL initialization?}}   {{reg32 |U HW_PLLAIEXT |R/W addr = 0x0d8001d0 |R/W hifields = 3 |R/W lofields = 1 |R/W |R/W 1 |R/W 1 |R/W 14|R/W |R/W ? |R/W ?|R/W ? || |A |B |HANG |D |E |16 ||? |F |G |DDR2|I }}Probably related to AI clocking.{{regdesc|DI2 A|DDR1Related to AI PLL initialization?|B|Related to AI PLL initialization?}}  {{reg32 | HW_PLLUSBEXT |1 addr = 0x0d8001d8 |1 hifields = 3 |lofields = 1 |1 |1 |1 |1 14|1 |1 R/W? |1 R/W?|1 ? |1 |1 A |1 B |1 |1 ||R/W 16 ||R/W ? |R/W |R/W |R/W |R/W }}Probably related to USB clocking.{{regdesc|R/W A|R/W Related to USB PLL initialization?|R/W B|R/W Related to USB PLL initialization?}} {{reg32 |R/W HW_VERSION |R/W addr = 0x0d800214 |R/W hifields = 1 |R/W lofields = 3 |R/W |R/W 16 ||L U |M |N |O |P |DI 8|R 4 |S 4 |T |U |SRSTR |HRSTR |V |SYS3|SYS2HWVER|SYS HWREV|
}}
This register seems to contain contains the RESET control bits for several parts hardware revision of the system, and possibly powerHollywood chipset. Observed values: * Hollywood ES1.x -on stuff too0x00 to 0x0f (?)<br>* Hollywood ES2. Reset/off = 0, run/on = - 0x10<br>* Hollywood ES2.1.- 0x11 
{{regdesc
|HANGHWVER|System reset without recovery? Kills DI, sets slot LED on, hangs starlet...Hollywood Version|DDR2HWREV|seems to be related to the GDDR3 memory|DI2|DI reset 2?|DDR1|seems to be related to the GDDR3 memory|P|If cleared, kills EXI-based starlet experimental proxy.|DI|DI reset|U|If cleared, kills EXI-based starlet experimental proxy.|V|Is cleared by IOS before modifying 1b8, and set again afterwards|SRST|PowerPC SRESET (release first)|HRST|PowerPC HRESET (release second)|SYS3|System reset 3. Also seems to reboot system.|SYS2|System reset 2. Also seems to reboot system.|SYS|System reset. Set to zero to reboot system.Hollywood Revision
}}
 
 
{{hwstub}}

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