10 bytes added ,  17:07, 10 August 2009
Robot: Cosmetic changes
Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.
The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.
==FIFO Setup==
{{reg16 | GX_CP_FIFO_STATUS | addr = 0xCC000000 | fields = 6 |
|11|1 |1 |1 |1 |1 |
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
{{regsimple | GX_PI_FIFO_WP | addr=0xCC003014 | bits=32 | access = R/W}}
===BP (blitting processor) registers===
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
More information on the [[Hardware/GX/Blitting_ProcessorBlitting Processor|BP]] can be found [[Hardware/GX/Blitting_ProcessorBlitting Processor|here]].
===CP (command processor) registers===
The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.
===XF (transform unit) registers===
The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.
More info on the XF can be found [[Hardware/GX/Transform Unit|here]].