Difference between revisions of "Hardware/Main Memory"

(add nfoz)
 
m (Capitalization, regs -> registers)
 
(5 intermediate revisions by 4 users not shown)
Line 11: Line 11:
 
| 0x00000000
 
| 0x00000000
 
| 24 MB
 
| 24 MB
| MEM1 Memory (Cached)
+
| MEM1 Memory
 
|-
 
|-
 
| 0x10000000
 
| 0x10000000
Line 17: Line 17:
 
| 0x10000000
 
| 0x10000000
 
| 64 MB
 
| 64 MB
| MEM2 Memory (Cached)
+
| MEM2 Memory
 
|-
 
|-
 
| 0x0D000000
 
| 0x0D000000
Line 23: Line 23:
 
| 0x0D000000
 
| 0x0D000000
 
|  
 
|  
| Hardware Registers (shared with the Broadway)
+
| Hardware Registers
 
|-
 
|-
 
| 0x0D400000
 
| 0x0D400000
Line 29: Line 29:
 
| 0x0D400000
 
| 0x0D400000
 
|  
 
|  
| RAM used for program code, data and stack
+
| Internal SRAM
 
|-
 
|-
 
| 0x0D800000
 
| 0x0D800000
Line 35: Line 35:
 
| 0x0D800000
 
| 0x0D800000
 
|  
 
|  
| Hardware Registers (Starlet private)
+
| Hardware Registers
 
|-
 
|-
| 0xFFFE0000
+
| 0xFFF00000
 
| 0xFFFFFFFF
 
| 0xFFFFFFFF
 
|  
 
|  
 
|  
 
|  
| Internal SRAM
+
| Internal SRAM (mirror)
 
|}
 
|}
  
I/O is at 0x0D800000 (Starlet private) and 0x0D000000 (shared with the Broadway). That is to say, the contents of 0x0D8xxxxx are selectively mirrored to 0x0D0xxxxx. This may change depending on some of the registers (e.g. when MIOS is active).
+
Hollywood I/O registers are at 0x0D80xxxx (Starlet private) and 0x0D00xxxx (shared with the Broadway). That is to say, the contents of 0x0D80xxxx are selectively mirrored to 0x0D0xxxxx. The Broadway "sees" 0x0D00xxxx when it tries to access 0x0D80xxxx (that address bit is forced to zero). This changes depending on some of the registers (e.g. when MIOS is active). Starlet private peripherals, however, live in 0x0D0yxxxx for y!=0 and the Broadway can't see them.
  
There is internal SRAM at 0xFFFE0000, 128kB of it; this stores the kernel code and data, minus the crypto code.
+
The GDDR3 is at 0x10000000, 64MB of it; a configurable range is exclusive for use by the Starlet (IOS reserves the top 12MB), the rest is shared with the Broadway.
  
The GDDR3 is at 0x10000000, 64MB of it; the upper 12MB are exclusive for use by the Starlet, the rest is shared with the Broadway.
+
0x0D0xxxxx may be an [http://www.arm.com/products/solutions/amba2overview.html AMBA AHB] bus.
  
0x0D0xxxxx may be an [http://www.arm.com/products/solutions/amba2overview.html AMBA AHB] bus.
+
The Starlet internal SRAM (96kB) mappings are weird (someone wikify this):
 +
 
 +
<pre><nowiki>
 +
SRAM and BOOT0 map into two main canonical areas (with tons of mirrors):
 +
- 0x0d400000 - 0x0d41ffff
 +
- 0xfffe0000 - 0xffffffff
 +
 
 +
Mirrors of note:
 +
 
 +
0xfff00000-0xfff1ffff is equivalent to 0x0d400000-0x0d41ffff.
 +
This is actually mirrored until 0xfffe0000 (or 0xffff0000 if you count half a mirroring block), where the mapping starts to differ.
 +
 
 +
BOOT0 runs from 0xffff0000 and loads BOOT1 into 0x0d400000, with HOLLYWOOD[0x60]&0x20 off
 +
BOOT1 runs from 0xfff00000 and 0x0d400000, with HOLLYWOOD[0x60]&0x20 off
 +
(BOOT1 seems to be compiled at 0x0d400000 but is called at 0xfff00000, so the program flow continuously switches between them as it goes through jump tables or back out through the stack and relative jumps)
 +
BOOT2LOADER runs from MEM1, switches HOLLYWOOD[0x60]&0x20 on, then loads BOOT2
 +
BOOT2/IOS runs from 0xffff0000, switches off BOOT0, then uses 0xfffe0000 as data RAM too, with HOLLYWOOD[0x60]&0x20 on
 +
 
 +
These are the maps:
 +
 
 +
--- BOOT0 enabled ---
 +
 
 +
HOLLYWOOD[0x60]&0x20 clear    HOLLYWOOD[0x60]&0x20 set
 +
 
 +
fff00000                      fff00000
 +
0d400000    fffe0000          0d400000    fffe0000
 +
+---------+  +---------+      +---------+  +---------+  +00000
 +
|        |  |        |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
| SRAM A  |  | SRAM A  |      |        |  |  BOOT0  |  +08000
 +
|        |  |        |      |        |  |  x8    |
 +
|        |  |        |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
+---------+  +---------+      |  BOOT0  |  +---------+  +10000
 +
|        |  |        |      |  x16  |  |        |
 +
| SRAM B  |  |        |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
+---------+  |  BOOT0  |      |        |  | SRAM A  |  +18000
 +
|        |  |  x8    |      |        |  |        |
 +
|  JUNK  |  |        |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
+---------+  +---------+      +---------+  +---------+  +20000
 +
 
 +
--- BOOT0 disabled ---
 +
 
 +
HOLLYWOOD[0x60]&0x20 clear    HOLLYWOOD[0x60]&0x20 set
 +
 
 +
fff00000                      fff00000
 +
0d400000    fffe0000          0d400000    fffe0000
 +
+---------+  +---------+      +---------+  +---------+  +00000
 +
|        |  |        |      |        |  |        |
 +
|        |  |        |      | SRAM B  |  | SRAM B  |
 +
|        |  |        |      |        |  |        |
 +
| SRAM A  |  | SRAM A  |      +---------+  +---------+  +08000
 +
|        |  |        |      |        |  |        |
 +
|        |  |        |      |  JUNK  |  |  JUNK  |
 +
|        |  |        |      |        |  |        |
 +
+---------+  +---------+      +---------+  +---------+  +10000
 +
|        |  |        |      |        |  |        |
 +
| SRAM B  |  | SRAM B  |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
+---------+  +---------+      | SRAM A  |  | SRAM A  |  +18000
 +
|        |  |        |      |        |  |        |
 +
|  JUNK  |  | JUNK    |      |        |  |        |
 +
|        |  |        |      |        |  |        |
 +
+---------+  +---------+      +---------+  +---------+  +20000
 +
 
 +
</nowiki></pre>
 +
 
 +
[[Category:Hardware]]

Latest revision as of 14:13, 16 September 2015

Start Address End Address Physical Address Size Description
0x00000000 0x017FFFFF 0x00000000 24 MB MEM1 Memory
0x10000000 0x13FFFFFF 0x10000000 64 MB MEM2 Memory
0x0D000000 0x0D000000 Hardware Registers
0x0D400000 0x0D400000 Internal SRAM
0x0D800000 0x0D800000 Hardware Registers
0xFFF00000 0xFFFFFFFF Internal SRAM (mirror)

Hollywood I/O registers are at 0x0D80xxxx (Starlet private) and 0x0D00xxxx (shared with the Broadway). That is to say, the contents of 0x0D80xxxx are selectively mirrored to 0x0D0xxxxx. The Broadway "sees" 0x0D00xxxx when it tries to access 0x0D80xxxx (that address bit is forced to zero). This changes depending on some of the registers (e.g. when MIOS is active). Starlet private peripherals, however, live in 0x0D0yxxxx for y!=0 and the Broadway can't see them.

The GDDR3 is at 0x10000000, 64MB of it; a configurable range is exclusive for use by the Starlet (IOS reserves the top 12MB), the rest is shared with the Broadway.

0x0D0xxxxx may be an AMBA AHB bus.

The Starlet internal SRAM (96kB) mappings are weird (someone wikify this):

SRAM and BOOT0 map into two main canonical areas (with tons of mirrors):
 - 0x0d400000 - 0x0d41ffff
 - 0xfffe0000 - 0xffffffff

Mirrors of note:

0xfff00000-0xfff1ffff is equivalent to 0x0d400000-0x0d41ffff.
This is actually mirrored until 0xfffe0000 (or 0xffff0000 if you count half a mirroring block), where the mapping starts to differ.

BOOT0 runs from 0xffff0000 and loads BOOT1 into 0x0d400000, with HOLLYWOOD[0x60]&0x20 off
BOOT1 runs from 0xfff00000 and 0x0d400000, with HOLLYWOOD[0x60]&0x20 off
(BOOT1 seems to be compiled at 0x0d400000 but is called at 0xfff00000, so the program flow continuously switches between them as it goes through jump tables or back out through the stack and relative jumps)
BOOT2LOADER runs from MEM1, switches HOLLYWOOD[0x60]&0x20 on, then loads BOOT2
BOOT2/IOS runs from 0xffff0000, switches off BOOT0, then uses 0xfffe0000 as data RAM too, with HOLLYWOOD[0x60]&0x20 on

These are the maps:

--- BOOT0 enabled ---

 HOLLYWOOD[0x60]&0x20 clear     HOLLYWOOD[0x60]&0x20 set

 fff00000                       fff00000
 0d400000     fffe0000          0d400000     fffe0000
+---------+  +---------+       +---------+  +---------+  +00000
|         |  |         |       |         |  |         |
|         |  |         |       |         |  |         |
|         |  |         |       |         |  |         |
| SRAM A  |  | SRAM A  |       |         |  |  BOOT0  |  +08000
|         |  |         |       |         |  |   x8    |
|         |  |         |       |         |  |         |
|         |  |         |       |         |  |         |
+---------+  +---------+       |  BOOT0  |  +---------+  +10000
|         |  |         |       |   x16   |  |         |
| SRAM B  |  |         |       |         |  |         |
|         |  |         |       |         |  |         |
+---------+  |  BOOT0  |       |         |  | SRAM A  |  +18000
|         |  |   x8    |       |         |  |         |
|  JUNK   |  |         |       |         |  |         |
|         |  |         |       |         |  |         |
+---------+  +---------+       +---------+  +---------+  +20000

--- BOOT0 disabled ---

 HOLLYWOOD[0x60]&0x20 clear     HOLLYWOOD[0x60]&0x20 set

 fff00000                       fff00000
 0d400000     fffe0000          0d400000     fffe0000
+---------+  +---------+       +---------+  +---------+  +00000
|         |  |         |       |         |  |         |
|         |  |         |       | SRAM B  |  | SRAM B  |
|         |  |         |       |         |  |         |
| SRAM A  |  | SRAM A  |       +---------+  +---------+  +08000
|         |  |         |       |         |  |         |
|         |  |         |       |  JUNK   |  |  JUNK   |
|         |  |         |       |         |  |         |
+---------+  +---------+       +---------+  +---------+  +10000
|         |  |         |       |         |  |         |
| SRAM B  |  | SRAM B  |       |         |  |         |
|         |  |         |       |         |  |         |
+---------+  +---------+       | SRAM A  |  | SRAM A  |  +18000
|         |  |         |       |         |  |         |
|  JUNK   |  | JUNK    |       |         |  |         |
|         |  |         |       |         |  |         |
+---------+  +---------+       +---------+  +---------+  +20000