Difference between revisions of "Hardware/Hollywood Registers"
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{{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}} | {{rla|0x0d800180|32|HW_DIFLAGS|Some DI stuff and boot code and {{check}}}} | ||
{{rla|0x0d80018c|32|HW_BOOT0|Maps boot0 {{check}}}} | {{rla|0x0d80018c|32|HW_BOOT0|Maps boot0 {{check}}}} | ||
− | {{rla|0x0d800194|32|HW_RESETS | + | {{rla|0x0d800194|32|HW_RESETS|System resets / power{{check}}}} |
{{rld|0x0d8001b4|32|HW_CLOCKS{{check}}|Clocking{{check}}}} | {{rld|0x0d8001b4|32|HW_CLOCKS{{check}}|Clocking{{check}}}} | ||
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}} | {{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}} |
Revision as of 19:28, 12 March 2009
Hollywood Registers | |
Access | |
---|---|
Broadway | Partial |
Starlet | Full |
Registers | |
Base | 0x0d800000 |
Length | 0x400 |
Access size | 32 bits |
Byte order | Big Endian |
IRQs | |
Broadway | 14 |
Hollywood | 0,10,11,17,30,31,...[check] |
The Hollywood chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the powerPC. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starlet permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
Register list
Hollywood Registers | |||
---|---|---|---|
Address | Bits | Name | Description |
0x0d800000 | 32 | HW_IPC_PPCMSG | IPC |
0x0d800004 | 32 | HW_IPC_PPCCTRL | |
0x0d800008 | 32 | HW_IPC_ARMMSG | |
0x0d80000c | 32 | HW_IPC_ARMCTRL | |
0x0d800010 | 32 | HW_TIMER | Starlet Timer |
0x0d800014 | 32 | HW_ALARM | |
0x0d800038 | 32 | HW_PPCIRQFLAG | Hollywood IRQ controller |
0x0d80003c | 32 | HW_PPCIRQMASK | |
0x0d800038 | 32 | HW_ARMIRQFLAG | |
0x0d80003c | 32 | HW_ARMIRQMASK | |
0x0d800038 | 32 | HW_MEMIRR | Memory control / SRAM bank swap[check] |
0x0d800070 | 32 | HW_EXICTRL | EXI PPC enable / control / other [check] |
0x0d8000c0 | 32 | HW_GPIOB_OUT | Hollywood GPIOs |
0x0d8000c4 | 32 | HW_GPIOB_DIR | |
0x0d8000c8 | 32 | HW_GPIOB_IN | |
0x0d8000cc | 32 | HW_GPIOB_INTLVL | |
0x0d8000d0 | 32 | HW_GPIOB_INTFLAG | |
0x0d8000d4 | 32 | HW_GPIOB_INTMASK | |
0x0d8000d8 | 32 | HW_GPIOB_INMIR | |
0x0d8000dc | 32 | HW_GPIO_ENABLE | |
0x0d8000e0 | 32 | HW_GPIO_OUT | |
0x0d8000e4 | 32 | HW_GPIO_DIR | |
0x0d8000e8 | 32 | HW_GPIO_IN | |
0x0d8000ec | 32 | HW_GPIO_INTLVL | |
0x0d8000f0 | 32 | HW_GPIO_INTFLAG | |
0x0d8000f4 | 32 | HW_GPIO_INTMASK | |
0x0d8000f8 | 32 | HW_GPIO_INMIR | |
0x0d8000fc | 32 | HW_GPIO_OWNER | |
0x0d800180 | 32 | HW_DIFLAGS | Some DI stuff and boot code and [check] |
0x0d80018c | 32 | HW_BOOT0 | Maps boot0 [check] |
0x0d800194 | 32 | HW_RESETS | System resets / power[check] |
0x0d8001b4 | 32 | HW_CLOCKS[check] | Clocking[check] |
0x0d8001ec | 32 | HW_OTPCMD | OTP |
0x0d8001d0 | 32 | HW_OTPDATA | |
0x0d800214 | 32 | HW_VERSION | Hollywood version |
General Registers
HW_VERSION (0x0d800214) | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | U | |||||||||||||||
Field | ||||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | U | R | R | |||||||||||||
Field | VERHI | VERLO |
This register contains the hardware revision of the Hollywood chipset.
Field | Description |
VERHI | Version |
VERLO | Revision |
HW_EXICTRL (0x0d800070) | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | ? | |||||||||||||||
Field | ||||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | ? | R/W | ||||||||||||||
Field | EXI |
This register controls at least the current EXI status.
Field | Description |
EXI | enable EXI bus |
HW_DIFLAGS (0x0d800180) | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | ? | R/W | ? | |||||||||||||
Field | PPCBOOT | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | ? | |||||||||||||||
Field |
This register seems to control some aspects of the powerpc booting and some di flags.[check]
Field | Description |
PPCBOOT | needs to be set to allow the powerpc to read the boot stub. |
HW_BOOT0 (0x0d80018c) | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | ? | |||||||||||||||
Field | ||||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | ? | R/W | ? | |||||||||||||
Field | BOOT0 |
This register at least control the boot0 memory mapping.
Field | Description |
BOOT0 | Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR |
HW_RESETS (0x0d800194) | ||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | U | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||||
Field | A | B | HANG | D | E | F | G | H | I | DI2 | K | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
Field | L | M | N | O | P | DI | R | S | T | U | PPC1 | PPC2 | V | SYS3 | SYS2 | SYS |
This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.
Field | Description |
HANG | System reset without recovery? Kills DI, sets slot LED on, hangs starlet... |
H | If cleared, kills EXI-based starlet experimental proxy. |
DI2 | DI reset 2? |
K | If cleared, kills EXI-based starlet experimental proxy. |
P | If cleared, kills EXI-based starlet experimental proxy. |
DI | DI reset |
U | If cleared, kills EXI-based starlet experimental proxy. |
PPC1 | PowerPC Reset 1 (release first) |
PPC2 | PowerPC Reset 2 (release second) |
SYS3 | System reset 3. Also seems to reboot system. |
SYS2 | System reset 2. Also seems to reboot system. |
SYS | System reset. Set to zero to reboot system. |
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