Hardware/Hollywood Registers

Hollywood Registers
Access
Broadway	Partial
Starlet	Full
Registers
Base	0x0d800000
Length	0x400
Access size	32 bits
Byte order	Big Endian
IRQs
Broadway	14
Hollywood	0,10,11,17,30,31,...[check]

The Hollywood chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the PowerPC. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starlet permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

See also the MINI source code, especially hollywood.h.

Register list

Hollywood Registers
Address	Bits	Name	Description
0x0d800000	32	HW_IPC_PPCMSG	IPC
0x0d800004	32	HW_IPC_PPCCTRL
0x0d800008	32	HW_IPC_ARMMSG
0x0d80000c	32	HW_IPC_ARMCTRL
0x0d800010	32	HW_TIMER	Starlet Timer
0x0d800014	32	HW_ALARM
0x0d800018	32	HW_PPCSPEED	PPC Speed Control
0x0d80001C	32	HW_VIDIM	Dims the video output
0x0d800024	32	HW_VISOLID	Sets the video output to a solid color
0x0d800030	32	HW_PPCIRQFLAG	Hollywood IRQ controller
0x0d800034	32	HW_PPCIRQMASK
0x0d800038	32	HW_ARMIRQFLAG
0x0d80003c	32	HW_ARMIRQMASK
0x0d800060	32	HW_MEMIRR	Memory control / SRAM bank swap[check]
0x0d800064	32	HW_AHBPROT	Access control for the PPC to access devices on the AHB
0x0d800070	32	HW_EXICTRL	EXI PPC enable / control / other [check]
0x0d800074	32	HW_DDRCTRL_ADDR	DDR Control
0x0d800076	32	HW_DDRCTRL_VAL
0x0d8000c0	32	HW_GPIOB_OUT	Hollywood GPIOs
0x0d8000c4	32	HW_GPIOB_DIR
0x0d8000c8	32	HW_GPIOB_IN
0x0d8000cc	32	HW_GPIOB_INTLVL
0x0d8000d0	32	HW_GPIOB_INTFLAG
0x0d8000d4	32	HW_GPIOB_INTMASK
0x0d8000d8	32	HW_GPIOB_INMIR
0x0d8000dc	32	HW_GPIO_ENABLE
0x0d8000e0	32	HW_GPIO_OUT
0x0d8000e4	32	HW_GPIO_DIR
0x0d8000e8	32	HW_GPIO_IN
0x0d8000ec	32	HW_GPIO_INTLVL
0x0d8000f0	32	HW_GPIO_INTFLAG
0x0d8000f4	32	HW_GPIO_INTMASK
0x0d8000f8	32	HW_GPIO_INMIR
0x0d8000fc	32	HW_GPIO_OWNER
0x0d800180	32	HW_DIFLAGS	Some DI stuff and boot code and [check]
0x0d800184	32	HW_UNKFLAGS	[check]
0x0d80018c	32	HW_BOOT0	Maps boot0 [check]
0x0d800190	32	HW_CLOCKS	clock stuff?
0x0d800194	32	HW_RESETS	System resets / power[check]
0x0d800198	32	HW_IFPOWER	set to 0xFFFFFF when Wii wakes up ("interfaces")
0x0d8001b0	32	HW_ACRPLLSYS	?
0x0d8001b4	32	HW_ACRPLLSYSEXT	Clocking?
0x0d8001dc	32	HW_SSPOWER	set to 0xFFFFFFF when Wii wakes up ("subsystems")
0x0d8001ec	32	HW_OTPCMD	OTP
0x0d8001f0	32	HW_OTPDATA
0x0d800214	32	HW_VERSION	Hollywood version
0x0d8b420a	16	MEM_PROT	MEM2 protection enable
0x0d8b420c	16	MEM_PROT_START	MEM2 protection low address (upper 16 bits)
0x0d8b420e	16	MEM_PROT_END	MEM2 protection high address (upper 16 bits
0x0d8b4228	16	MEM_FLUSHREQ	AHB flush request
0x0d8b422a	16	MEM_FLUSHACK	AHB flush ack

General Registers

HW_VERSION (0x0d800214)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	U
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	U								R				R
Field									VERHI				VERLO

This register contains the hardware revision of the Hollywood chipset.

Field	Description
VERHI	Version
VERLO	Revision

HW_VIDIM (0x0d80001c)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?								R/W	R/W	R/W			R/W
Field									E		Y			C

This register controls dimming of the video output.

Field	Description
E	Turns Dimming on/off
Y	Amount to dim luma component (0-7)
C	Amount to dim chroma components (0-7)

HW_VISOLID (0x0d800024)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R/W								R/W
Field	U								V
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W								?							R/W
Field	Y															E

This register controls the solid color for VI.

Field	Description
U	U component
V	V component
Y	Luma component
E	Turns solid colour on/off

HW_EXICTRL (0x0d800070)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?											R/W	?			R/W
Field												DI				EXI

This register controls at least the current EXI status.

Field	Description
DI	unknown, used with DI-only syscalls 52 and 53, and appears to always be cleared[check]
EXI	enable EXI bus

HW_DIFLAGS (0x0d800180)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?										R/W	R/W	?
Field											DVDVIDEO	PPCBOOT
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?													R/W	R/W	?
Field														?	?

This register seems to control some aspects of the PowerPC booting and some DI flags.^[check]

Field	Description
DVDVIDEO	Disables[check] DVD video support when set
PPCBOOT	needs to be set to allow the PowerPC to read the boot stub.
Bit 3	unknown
Bit 2	when clear, disables bit 14 in the PPC IRQ flags

HW_BOOT0 (0x0d80018c)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?	R/W		R/W	?
Field		DSKPLLSRC		BOOT0

This register at least controls the boot0 memory mapping and DSK PLL source.

Field	Description
BOOT0	Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_MEMMIRR
DSKPLLSRC	According to STM, setting this to 00 "puts DSKPLL back to external reference"

HW_CLOCKS (0x0d800190)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?														R/W	R/W
Field															SPEED	FX

This register is involved in some sort of clocking.

Field	Description
FX	Unknown, but IOS calls this "FX".
SPEED	Sets the Hollywood clock to 243MHz when 0 (Wii mode) or 162MHz when 1 (GC mode)

HW_ACRPLLSYS (0x0d8001b0)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?					R/W?									?
Field						clk_0
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?
Field

This register is involved in some sort of clocking.

Field	Description
clk_0	Unknown, but IOS calls this "clk_0".

HW_ACRPLLSYSEXT (0x0d8001b4)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access								R/W?
Field								clk_1

This register is involved in some sort of clocking.

Field	Description
clk_1	Unknown, but IOS calls this "clk_1".

HW_RESETS (0x0d800194)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	U					R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Field						NLCKB_EDRAM	RSTB_EDRAM	RSTB_AHB	RSTB_IOP	RSTB_DSP	RSTB_VI1	RSTB_VI	RSTB_IOPI	RSTB_IOMEM	RSTB_IODI	RSTB_IOEXI
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Field	RSTB_IOSI	RSTB_AI_I2S3	RSTB_GFX	RSTB_GFXTCPE	RSTB_MEM	RSTB_DIRSTB	RSTB_PI	RSTB_MEMRSTB	NLCKB_SYSPLL	RSTB_SYSPLL	SRSTB_CPU	RSTB_CPU	RSTB_DSKPLL	RSTB_MEMRSTB	CRSTB	RSTBINB

This register seems to contain the RESET control bits for several parts of the system, and possibly power-on stuff too. Reset/off = 0, run/on = 1.

Field	Description
NLCKB_EDRAM	Unlock external DRAM reset?
RSTB_EDRAM	External DRAM reset
RSTB_AHB	ARM AHB reset. Kills DI, sets slot LED on, hangs starlet...
RSTB_IOP	IOP/Starlet reset
RSTB_VI1	VI1 reset?
RSTB_VI	Video Interface reset
RSTB_IOPI	Processor Interface IO reset
RSTB_IOMEM	MEM IO reset
RSTB_IODI	Disk Interface IO reset
RSTB_IOEXI	EXI IO reset
RSTB_IOSI	SI IO reset
RSTB_AI_I2S3	Audio interface I2S3 reset
RSTB_GFX	GFX reset?
RSTB_GFXTCPE	GFX TCPE?
RSTB_MEM	MEM reset. If cleared, kills EXI-based starlet experimental proxy.
RSTB_DIRSTB	Disk Interface reset BToo many fields, User:Marcan is lazy, please update Template:reglist.