Difference between revisions of "Hardware/GX"

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{{hwstub}}
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{{yagcd}}
 
{{Infobox MMIO
 
{{Infobox MMIO
 
| title = Pixel Engine
 
| title = Pixel Engine
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| ppcirq = 9,10
 
| ppcirq = 9,10
 
}}
 
}}
{{Infobox MMIO
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| title = Command Processor
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The '''GX''' is the [[Wii]]'s GPU, hidden inside [[Hollywood]], what Nintendo claims to be the GPU. Its graphics capabilities are similar to that of the GameCube's Flipper, except running at a higher clock speed.
| ppc = Full
+
 
| base = 0x0c000000
 
| len = 0x80
 
| bits = 16
 
| ppcirq = 11
 
}}
 
{{hwstub}}
 
{{yagcd}}
 
 
== GX FIFO ==
 
== GX FIFO ==
Graphics processor commands can be 8bit or 32bit, but they must be sent 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.
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Graphics processor commands can be 8bit or 32bit, but they must be sent padded to 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.
  
 
The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.
 
The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.
== FIFO Setup ==
 
{{reg16 | GX_CP_FIFO_STATUS | addr = 0xCC000000 | fields = 6 |
 
|11|1    |1      |1    |1 |1 |
 
|U |R    |R      |R    |R |R |
 
|  |BPInt|CmdIdle|RdIdle|UF|OF|
 
|}}
 
{{regdesc
 
|BPInt|Indicates status of Blitting Processor interrupt?
 
|CmdIdle|1: CP is not doing anything
 
|RdIdle|1: CP is not reading anything (??)
 
|UF|FIFO underflow (Determined by watermark registers?
 
|OF|FIFO overflow ("")
 
}}
 
{{reg16 | GX_CP_CONTROL | addr = 0xCC000002 | fields = 7 |
 
|10|1  |1  |1    |1    |1    |1    |
 
|U |R/W|R/W |R/W  |R/W  |R/W  |R/W  |
 
|  |BPE|GPLE|UFInt|OFInt|CPInt|FIFOE|
 
|}}
 
{{regdesc
 
|BPE|breakpoint enable (default 0)
 
|GPLE|FIFO link enable (YAGCD says CP->PE?) (default 1)
 
|UFInt|FIFO underflow interrupt (default 0)
 
|OFInt|FIFO overflow interrupt (default 1)
 
|CPInt|Command Processor interrupt (default 0)
 
|FIFOE|FIFO read enable (disable while setting up) (default 1)
 
}}
 
{{regsimple | GX_CP_FIFO_START  | addr=0xCC000020 | bits=32 | access = R/W}}
 
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
 
{{regsimple | GX_CP_FIFO_END    | addr=0xCC000024 | bits=32 | access = R/W}}
 
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
 
{{regsimple | GX_CP_FIFO_WP      | addr=0xCC000034 | bits=32 | access = R/W}}
 
WARNING: This CP register is actually two 16 bit registers. Though it is big endian, a bug in the hardware means the two 16 bit halves will be swapped if you write to it 32-bit. You have been warned!
 
{{regsimple | GX_PI_FIFO_WP      | addr=0xCC003014 | bits=32 | access = R/W}}
 
 
=== BP (blitting processor) registers ===
 
=== BP (blitting processor) registers ===
 
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
 
The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value.
More information on the [[Hardware/GX/Blitting Processor|BP]] can be found [[Hardware/GX/Blitting Processor|here]].
+
More information on the BP can be found [[Hardware/GX/Blitting Processor|here]].
  
 
=== CP (command processor) registers ===
 
=== CP (command processor) registers ===
The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something.
+
The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. More information on the CP can be found [[Hardware/GX/Command Processor|here]].
 
=== XF (transform unit) registers ===
 
=== XF (transform unit) registers ===
 
The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.
 
The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas.
 
More info on the XF can be found [[Hardware/GX/Transform Unit|here]].
 
More info on the XF can be found [[Hardware/GX/Transform Unit|here]].
 
== GX Development ==
 
* [http://gxr.brickmii.com/Tutorial/ Incomplete tutorial]
 

Latest revision as of 18:05, 29 March 2021

Pixel Engine
Access
BroadwayFull
StarletNone
Registers
Base0x0c001000
Length0x100
Access size32 bits
Byte orderBig Endian
IRQs
Broadway9,10
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The GX is the Wii's GPU, hidden inside Hollywood, what Nintendo claims to be the GPU. Its graphics capabilities are similar to that of the GameCube's Flipper, except running at a higher clock speed.

GX FIFO

Graphics processor commands can be 8bit or 32bit, but they must be sent padded to 32bit. The CPU has a 32-bit FIFO accessed through the WGPIPE register at 0xcc008000 that will automatically pack data for you. All sorts of graphics data (vertices, primitives, etc) are sent through the FIFO.

The FIFO is a ring buffer in main memory. It is similar that it can be placed anywhere in main memory. One needs to initialize CP registers to describe the FIFO. Afterwards, all communications to the CP (including those forwarded to other units) are performed through the FIFO.

BP (blitting processor) registers

The BP registers are accessed by writing a 8-bit value of 0x61 to the FIFO, followed by 32 bit value. This value is a bit weird - the high 8 bits are the register, and the low 24 bits are the register value. More information on the BP can be found here.

CP (command processor) registers

The (internal, there are other CP registers mapped to main memory) CP registers are accessed by writing a 8-bit 0x08 to the FIFO, followed by 8 bits of something and then 32 bits of something. More information on the CP can be found here.

XF (transform unit) registers

The XF registers are accessed by first writing an 8-bit number of 0x10 to the FIFO, then a 32 bit value whose lower 16 bits are the address, and the upper 16 bits are the number of addresses to write to - 1. Following is one or more 32 bit datas. More info on the XF can be found here.