| EXI
|
| Address
|
Bits
|
Name
|
Description
|
| 0x0d806800
|
32
|
EXI0_CSR
|
EXI Channel 0 Parameter Register (Status?)
|
| 0x0d806800
|
32
|
EXI0_MAR
|
EXI Channel 0 DMA Start Address
|
| 0x0d806800
|
32
|
EXI0_LENGTH
|
EXI EXI Channel 0 DMA Transfer Length
|
| 0x0d806800
|
32
|
EXI0_CR
|
EXI Channel 0 Control Register
|
| 0x0d806810
|
32
|
EXI0_DATA
|
EXI Channel 0 Immediate Data
|
| 0x0d806814
|
32
|
EXI1_CSR
|
EXI Channel 1 Parameter Register (Status?)
|
| 0x0d806818
|
32
|
EXI1_MAR
|
EXI Channel 1 DMA Start Address
|
| 0x0d80681c
|
32
|
EXI1_LENGTH
|
EXI EXI Channel 1 DMA Transfer Length
|
| 0x0d806820
|
32
|
EXI0_CR
|
EXI Channel 1 Control Register (Status?)
|
| 0x0d806824
|
32
|
EXI0_DATA
|
EXI Channel 1 Immediate Data
|
| 0x0d806828
|
32
|
EXI2_CSR
|
EXI Channel 2 Parameter Register (Status?)
|
| 0x0d80682c
|
32
|
EXI2_MAR
|
EXI Channel 2 DMA Start Address
|
| 0x0d806830
|
32
|
EXI2_LENGTH
|
EXI EXI Channel 2 DMA Transfer Length
|
| 0x0d806834
|
32
|
EXI2_CR
|
EXI Channel 2 Control Register (Status?)
|
| 0x0d806838
|
32
|
EXI2_DATA
|
EXI Channel 2 Immediate Data
|
Parameter Register
| EXIX_CSR
|
|
|
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
| Access
|
|
| Field
|
|
|
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0
|
| Access
|
1
|
|
R/W
|
R/W
|
R/W
|
R/W
|
R/W
|
R/W
|
R/W
|
| Field
|
B15
|
B14
|
B13
|
B12
|
B11
|
B10
|
B9
|
B8
|
B7
|
This register at least controls the boot0 memory mapping and DSK PLL source.
| Field
|
Description
|
| ROMDIS
|
(EXI0 only) 1: rom de-scramble logic disabled (*1)
|
| EXT
|
Device Connected Bit (R) 1 if a device is connected on the specific channel
|
| EXTINT
|
External Insertion Interrupt Status
- When read 1 or 0 indicates if interrupt is requested
- When 1 is written to this register, it clears the interrupt
|
| EXTINTMASK
|
EXT Interrupt Mask (1 - enable, 0 - disable) (*5)
|
| CS
|
devices selected on this channel, each bit selecting one device. (*)
|
| CLK
|
used frequency
000 = 1MHz
001 = 2MHz
010 = 4MHz
011 = 8MHz
100 = 16MHz
101 = 32MHz
110 = reserved
111 = reserved |
| TCINT
|
Transfer Complete Interrupt Status
- When read 1 or 0 indicates if interrupt is requested
- When 1 is written to this register, it clears the interrupt
|
| TCINTMASK
|
Transfer complete interrupt mask (1 - enable, 0 - disable) (*2)
|
| EXTINT
|
Interrupt Status
- When read 1 or 0 indicates if interrupt is requested
- When 1 is written to this register, it clears the interrupt
|
| EXTINTMASK
|
EXI interrupt mask (1 - enable, 0 - disable)
|
As mentioned, there is small amount of memory in the EXI that is used as the PowerPC reset vector.
IOS's function to initialize the EXI reset vector has 2 default boot vectors depending on the parameters, but a custom boot vector is used by the IOS_StartPPC syscall.
| Start Address
|
End Address
|
Size
|
Description
|
| 0x0d806840
|
0x0d806880
|
0x40
|
PPC Reset vector
|
IOS_StartPPC vector
fff00100 3c 60 00 00 lis r3, 0
fff00104 60 63 34 00 ori r3, r3, 0x3400
fff00108 7c 7a 03 a6 mtspr SRR0, r3
fff0010c 38 60 00 00 li r3, 0
fff00110 7c 7b 03 a6 mtspr SRR1, r3
fff00114 4c 00 00 64 rfi
Default vector (with HID4 initialization)
fff00100 7c 63 1a 78 xor r3, r3, r3
fff00104 64 63 d7 b0 oris r3, r3, 0xd7b0
fff00108 7c 73 fb a6 mtspr HID4, r3
fff0010c 4c 00 01 2c isync
fff00110 3c 40 00 00 lis r2, 0x0
fff00114 60 42 01 00 ori r2, r2, 0x100
fff00118 7c 5a 03 a6 mtspr SRR0, r2
fff0011c 38 a0 00 00 li r5, 0
fff00120 7c bb 03 a6 mtspr SRR1, r5
fff00124 4c 00 00 64 rfi
fff00128 60 00 00 00 nop
fff0012c 60 00 00 00 nop
fff00130 60 00 00 00 nop
Default vector (without HID4 initialization)
fff00100 7c 63 1a 78 xor r3, r3, r3
fff00104 7c 73 fb a6 mtspr HID4, r3
fff00108 4c 00 01 2c isync
fff0010c 3c 40 00 00 lis r2, 0
fff00110 60 42 01 00 ori r2, r2, 0x100
fff00114 7c 5a 03 a6 mtspr SRR0, r2
fff00118 38 a0 00 00 li r5, 0
fff0010c 7c bb 03 a6 mtspr SRR1, r5
fff00120 4c 00 00 64 rfi
fff00124 60 00 00 00 nop
fff00128 60 00 00 00 nop
fff0012c 60 00 00 00 nop