892
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Changes
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}}
}}
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−{{regsimple | AES_SRC | addr = 0x0d020004 | bits = 32 | access = R/W }}
+{{regsimple2 | AES_SRC | addr = 0x0d020004 | bits = 32 | split=4 | access = U | accesshi = R/W }}
−This register contains the DMA address of the source data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
+This register contains the DMA address of the source data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
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−{{regsimple | AES_SRC | addr = 0x0d020008 | bits = 32 | access = R/W }}
+{{regsimple2 | AES_DEST | addr = 0x0d020008 | bits = 32 | split=4 | access = U | accesshi = R/W}}
−This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
+This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
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{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}