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Difference between revisions of "Hardware/NAND Interface"

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(Undo revision 88046 by Cease and Desist (Talk))
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This is a warning to the owners of this site. My name is Shigeru Miyamoto and I am disappoint. You are breaking the DCMA laws. DCMA laws protect our freedoms far into the furture. There is over 9000 pages here and I want every single one of them gone by next week. This is not a threat but a promise. Every day after that week is up, I will sue you for $100,000 a day.
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{{Infobox MMIO
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| arm = Full
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Thank you for using Nintendo. We must ensure our freedoms through use of the DCMA. This not the analog millennium one passed in 1000 A.D., but the digital one.
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| base = 0x0d010000
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| len = 0x1C
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==CEASE==
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| bits = 32
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AND DESIST
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| hwdirq = 1
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}}
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== Register List ==
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{{reglist|NAND Interface}}
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{{rla|0x0d010000|32|NAND_CTRL|NAND Control and Status}}
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{{rla|0x0d010004|32|NAND_CONFIG|??}}
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{{rla|0x0d010008|32|NAND_ADDR1|Address bytes 1-2 (column)}}
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{{rla|0x0d01000c|32|NAND_ADDR2|Address bytes 3-5 (row)}}
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{{rla|0x0d010010|32|NAND_DATABUF|Memory address of the Data buffer}}
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{{rla|0x0d010014|32|NAND_ECCBUF|Memory address of the Spare buffer}}
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{{rla|0x0d010018|32|NAND_UNK|Unknown}}
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|}
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== Register Details ==
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{{reg32 | NAND_CTRL | addr = 0x0d010000 | hifields = 9 | lofields = 5 |
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|1|1|1|1|1|1|1|1|8|
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|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|R/W|
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|EXEC|IRQ|ERR|A5|A4|A3|A2|A1|COMMAND||
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|1|1|1|1|12|
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|R/W|R/W|R/W|R/W|W|
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|WAIT|WR|RD|ECC|DATALEN|
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}}
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This register controls the state of the NAND interface.
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{{regdesc
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|EXEC|Write 1: initiate NAND command<br/>Write 0: reset NAND interface<br/>Read: NAND interface busy
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|IRQ|Set to enable IRQ generation when command is complete
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|ERR|If set, NAND error occured (?){{check}}
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|A5|Send fifth address byte (typ. row address high)
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|A4|Send fourth address byte (typ. row address mid)
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|A3|Send third address byte (typ. row address low)
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|A2|Send second address byte (typ. column address high)
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|A1|Send first address byte (typ. column address low)
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|COMMAND|8-bit NAND command
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|WAIT|Wait for R/B to go high between address and data phases (wait for read/write/erase/reset)
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|WR|Transfer data to the NAND chip
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|RD|Transfer data from the NAND chip
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|ECC|Calculate ECC or ?? {{check}}
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|DATALEN|Number of bytes to transfer during the data phase
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}}
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----
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{{reg32 | NAND_CONFIG | addr = 0x0d010004 | hifields = 4 | lofields = 2 |
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|4|1|4|8|
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|R/W|R/W|R/W|R/W|
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|ATTR0|ENABLE|ATTR1|ATTR2||
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|8|8|
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|R/W|R/W|
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|ATTR3|ATTR4|
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}}
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This register probably configures certain aspects of the NAND interface (timings?){{check}}.  
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{{regdesc
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|ATTR0|Set based on lookup table; set to 3 for 128MB NAND chips, 4 otherwise
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|ENABLE|Set to 1 before first command is sent to NAND, set to 0 when de-initializing the NAND driver.
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|ATTR1|Set based on lookup table; always 0x3
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|ATTR2|Set based on lookup table; always 0x3e
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|ATTR3|Set based on lookup table; always 0x0e
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|ATTR4|Set based on lookup table; always 0x7f
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}}
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When IOS initializes the NAND driver, it turns on the enable bit (writing 0x08000000) and then send the GET CHIP ID command (0x90). Based on the reply, it looks up the correct definitions of the other attributes and pokes them into this register (generally, 0x4b3e0e7f).
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----
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{{reg32 | NAND_ADDR1 | addr = 0x0d010008 | hifields = 1 | lofields = 2 |
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|16|
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|U|
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|||
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|8|8|
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|R/W|R/W|
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|ADDR2|ADDR1|
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}}
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This register contains the first two address bytes that can be sent to the NAND chip. Normally it contains the column address (offset within a page).
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{{regdesc
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|ADDR2|Second address byte
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|ADDR1|First address byte
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}}
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----
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{{reg32 | NAND_ADDR2 | addr = 0x0d01000c | hifields = 2 | lofields = 2 |
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|8|8|
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|U|R/W|
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||ADDR5||
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|8|8|
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|R/W|R/W|
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|ADDR4|ADDR3|
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}}
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This register contains the last three address bytes that can be sent to the NAND chip. Normally it contains the row address (page number).
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{{regdesc
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|ADDR5|Fifth address byte
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|ADDR4|Fourth address byte
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|ADDR3|Third address byte
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}}
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----
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{{regsimple2 | NAND_DATABUF | addr = 0x0d010010 | bits = 32 | split=4 | access = U | accesshi = R/W }}
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This register contains the DMA address of the page data buffer (0x800 bytes). The address must be 16-byte aligned.
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If the spare data is being written alone (such as using a RANDOM DATA IN command with DMALEN=0x40), this points to it instead. Generally speaking, the first 0x800 bytes of data go here, whatever they may be.
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----
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{{regsimple2 | NAND_ECCBUF | addr = 0x0d010014 | bits = 32 | split=4 | access = U | accesshi = R/W }}
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This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome). The address must be 16-byte aligned.
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The hardware-calculated ECC is written to the address in this register XOR 0x40.
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----
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{{regsimple | NAND_UNK | addr = 0x0d010018 | bits = 32 | access = R/W }}
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This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.

Revision as of 21:17, 7 August 2010

NAND Interface
Access
BroadwayNone
StarletFull
Registers
Base0x0d010000
Length0x1C
Access size32 bits
Byte orderBig Endian
IRQs
Hollywood1
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Register List

NAND Interface
Address Bits Name Description
0x0d010000 32 NAND_CTRL NAND Control and Status
0x0d010004 32 NAND_CONFIG ??
0x0d010008 32 NAND_ADDR1 Address bytes 1-2 (column)
0x0d01000c 32 NAND_ADDR2 Address bytes 3-5 (row)
0x0d010010 32 NAND_DATABUF Memory address of the Data buffer
0x0d010014 32 NAND_ECCBUF Memory address of the Spare buffer
0x0d010018 32 NAND_UNK Unknown

Register Details

NAND_CTRL (0x0d010000)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
Field EXEC IRQ ERR A5 A4 A3 A2 A1 COMMAND
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W R/W R/W W
Field WAIT WR RD ECC DATALEN

This register controls the state of the NAND interface.

Field Description
EXEC Write 1: initiate NAND command
Write 0: reset NAND interface
Read: NAND interface busy
IRQ Set to enable IRQ generation when command is complete
ERR If set, NAND error occured (?)[check]
A5 Send fifth address byte (typ. row address high)
A4 Send fourth address byte (typ. row address mid)
A3 Send third address byte (typ. row address low)
A2 Send second address byte (typ. column address high)
A1 Send first address byte (typ. column address low)
COMMAND 8-bit NAND command
WAIT Wait for R/B to go high between address and data phases (wait for read/write/erase/reset)
WR Transfer data to the NAND chip
RD Transfer data from the NAND chip
ECC Calculate ECC or ?? [check]
DATALEN Number of bytes to transfer during the data phase

NAND_CONFIG (0x0d010004)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W R/W R/W R/W
Field ATTR0 ENABLE ATTR1 ATTR2
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field ATTR3 ATTR4

This register probably configures certain aspects of the NAND interface (timings?)[check].

Field Description
ATTR0 Set based on lookup table; set to 3 for 128MB NAND chips, 4 otherwise
ENABLE Set to 1 before first command is sent to NAND, set to 0 when de-initializing the NAND driver.
ATTR1 Set based on lookup table; always 0x3
ATTR2 Set based on lookup table; always 0x3e
ATTR3 Set based on lookup table; always 0x0e
ATTR4 Set based on lookup table; always 0x7f

When IOS initializes the NAND driver, it turns on the enable bit (writing 0x08000000) and then send the GET CHIP ID command (0x90). Based on the reply, it looks up the correct definitions of the other attributes and pokes them into this register (generally, 0x4b3e0e7f).

NAND_ADDR1 (0x0d010008)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field ADDR2 ADDR1

This register contains the first two address bytes that can be sent to the NAND chip. Normally it contains the column address (offset within a page).

Field Description
ADDR2 Second address byte
ADDR1 First address byte

NAND_ADDR2 (0x0d01000c)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U R/W
Field ADDR5
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R/W R/W
Field ADDR4 ADDR3

This register contains the last three address bytes that can be sent to the NAND chip. Normally it contains the row address (page number).

Field Description
ADDR5 Fifth address byte
ADDR4 Fourth address byte
ADDR3 Third address byte

NAND_DATABUF (0x0d010010)
  314 30
Access R/W U

This register contains the DMA address of the page data buffer (0x800 bytes). The address must be 16-byte aligned. If the spare data is being written alone (such as using a RANDOM DATA IN command with DMALEN=0x40), this points to it instead. Generally speaking, the first 0x800 bytes of data go here, whatever they may be.

NAND_ECCBUF (0x0d010014)
  314 30
Access R/W U

This register contains the DMA address of the spare and ECC data buffer (0x40 spare bytes + 0x10 bytes of hardware-calculated ECC syndrome). The address must be 16-byte aligned. The hardware-calculated ECC is written to the address in this register XOR 0x40.

NAND_UNK (0x0d010018)
  310
Access R/W

This register has an unknown function; boot2 writes 1 to it when reloading to a new IOS.

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