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| − | This page lists the known [[Starlet]] I/O registers. Much of this info comes from Segher & tmbinc's private notes.
| + | #REDIRECT [[Hollywood/Registers]] |
| − | | |
| − | == IO Memory ==
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| − | | |
| − | {| class="wikitable"
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| − | ! base
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| − | ! function
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| − | ! offset
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| − | ! description
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| − | ! contents/example
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| − | |-
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| − | |0x0D800000
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| − | | hollywood control
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| − | | 0x400 bytes of control registers; these registers are mirrored every 0x400 bytes from 0x0D80000 to 0x0D805fff
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| − | |
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| − | |
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| − | |-
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| − | |0x0D800000
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| − | |IPC
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| − | |
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| − | | reg 0: request pointer
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| − | | To make an IOS request, the physical address of an IOS command struct is written here by the Broadway. Then, Broadway sets bit 0 of IPC reg 1 to indicate a request is ready.
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| − | |-
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| − | |0x0D800004
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| − | |IPC
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| − | |
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| − | | reg 1: semaphore flags
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| − | | Broadway sets bits here as "doorbells" to indicate status; Starlet responds by setting flags here.
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| − | |-
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| − | |0x0D800008
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| − | |IPC
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| − | |
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| − | |reg 2: Reply pointer
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| − | | When an IOS request has completed, IOS will modify the original command struct passed in IPC reg 0, copy that pointer to reg 2, then set reg 1 to 0x14 to indicate a reply is ready.
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| − | |-
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| − | |0x0D800010
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| − | |timer (core clock divided by 128)
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D800014
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| − | | alarm (interrupt 0 is fired when the timer reaches this value)
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D800030
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| − | | something related to interrupts; typical value is 0x854DA94F. Pressing the RESET button will set the 0x20000 bit.
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D800034
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| − | |???
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D800038
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| − | |active interrupts (write 1 to clear). Pressing the RESET button will set the 0x20000 bit (interrupt 18). Pressing the POWER button will set the 0x800 bit (interrupt 11).
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| − | |
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| − | |
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| − | |-
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| − | |0x0D80003C
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| − | |enabled interrupts
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| − | |
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| − | |
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| − | | clear 0x40000 for legacy di
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| − | |-
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| − | |0x0D800060
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| − | |???
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | 0x0D800070
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| − | |???
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| − | |
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| − | |
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| − | | set 0x10 for legacy DI; 0x1 to allow write to exi boot buffer
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| − | |-
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| − | |0x0D8001EC
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| − | |OTP
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| − | |
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| − | |
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| − | | OTP read address (addresses run from 0x80000000..0x8000001F)
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| − | |-
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| − | |
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| − | |
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| − | | 0x80000000 - 0x80000004 stores 20 bytes boot1 SHA-1 hash
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| − | |-
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| − | | 0x80000005 - 0x80000008 common key
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| − | |-
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| − | | 0x80000009 NG id
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| − | |-
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| − | | 0x8000000a - 0x80000010 NG private
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| − | |-
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| − | | 0x80000011 - 0x80000015 NAND HMAC
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| − | |-
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| − | | 0x80000016 - 0x80000019 NAND AES
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| − | |-
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| − | | 0x8000001A - 0x8000001D RNG key
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| − | |-
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| − | |0x0D8001F0
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| − | |OTP
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| − | |
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| − | |
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| − | | OTP data
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| − | |-
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| − | |0x0D800214
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| − | |???
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| − | |
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| − | |
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| − | | Register is read 223 times while booting boot0 and boot1. Never written by boot0 or boot1.
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| − | |-
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| − | |0x0D800224 - 03FF
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| − | |
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| − | |
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| − | | unused
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| − | |
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| − | |-
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| − | |0x0D806800
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| − | |EXI
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| − | | 0x40
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| − | | ppc boot buffer
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| − | |
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| − | |-
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| − | |0x0D8B4000
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| − | | AMBA AHB registers
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4000
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| − | |???
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4002
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| − | |???
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4004
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| − | |???
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4006
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| − | |???
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| − | |
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| − | |-
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| − | |0x0D8B4008
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| − | |???
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| − | |
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| − | |-
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| − | |0x0D8B400A
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| − | |???
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| − | |-
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| − | |0x0D8B400C
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| − | |???
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| − | |-
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| − | |0x0D8B400E
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| − | |???
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| − | |-
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| − | |0x0D8B4026
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| − | |???
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4074
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| − | |???
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4076
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| − | |???
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| − | |
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| − | |
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| − | |
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| − | |-
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| − | |0x0D8B4228
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| − | | AHB command
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| − | | AHB memory flush command. Typical values: 1, 2, 4, 8, 15
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| − | |-
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| − | |0x0D8B422a
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| − | | AHB acknowlegde
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| − | | If AHB memory flush acknowledge, will be set to the command value.
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| − | |}
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| − | [[Category:Hardware]]
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