In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/Memory Controller"

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Line 7: Line 7:
 
| len = 0xcc (?)
 
| len = 0xcc (?)
 
| bits = 16
 
| bits = 16
−
}}
 
−
 
−
{{Infobox MMIO
 
−
| title = SEQ
 
−
| arm = Full
 
−
| ppc = ???
 
−
| base = N/A
 
−
| len = ???
 
−
| bits = 16
 
−
}}
 
−
 
−
{{Infobox MMIO
 
−
| title = BIST
 
−
| arm = Full
 
−
| ppc = ???
 
−
| base = N/A
 
−
| len = ???
 
−
| bits = 16
 
−
}}
 
−
 
−
{{Infobox MMIO
 
−
| title = PERF
 
−
| arm = Full
 
−
| ppc = ???
 
−
| base = N/A
 
−
| len = ???
 
−
| bits = 16
 
−
}}
 
−
 
−
{{Infobox MMIO
 
−
| title = ARB_EX (?)
 
−
| arm = ???
 
−
| ppc = ???
 
−
| base = ???
 
−
| len = ???
 
−
| bits = ???
 
 
}}
 
}}
  
Line 51: Line 15:
 
The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
 
The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.
  
−
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers.
+
Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers:
−
Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of these indirect accesses are
+
 
 +
* For the DDR SEQ registers, MEM_SEQ_ADDR and MEM_SEQ_DATA
 +
* For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA
 +
* For the DPERF registers, presumably MEM_PERF and MEM_PERF_READ are involved {{check}}
 +
* MEM_ARB_EXADDR and MEM_ARB_EXCMD are used during DRAM initialization for Mode Register Set programming (the layout is probably vendor-specific).
 +
 
 +
Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are
 
performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].
 
performed starting with another pair in the [[Hardware/Memory_Interface|Memory Interface registers]].
  
Line 131: Line 101:
 
|}
 
|}
  
−
== DDR SEQ Register Space ==
+
= DDR SEQ Register Space =
 +
{{Infobox MMIO
 +
| title = SEQ
 +
| arm = Full
 +
| ppc = ???
 +
| base = N/A
 +
| len = ???
 +
| bits = 16
 +
}}
 +
''Note: These registers are NOT mapped into memory.''
 +
{{reglist|DDR SEQ Registers}}
  
 +
{{rld|0x00000000|16|DDR_SEQ_BL4||}}
 +
{{rld|0x00000001|16|DDR_SEQ_TRCDR||}}
 +
{{rld|0x00000002|16|DDR_SEQ_TRCDW||}}
 +
{{rld|0x00000003|16|DDR_SEQ_TRAS||}}
 +
{{rld|0x00000004|16|DDR_SEQ_TRC||}}
 +
{{rld|0x00000005|16|DDR_SEQ_TCL||}}
 +
{{rld|0x00000006|16|DDR_SEQ_TWL||}}
 +
{{rld|0x00000007|16|DDR_SEQ_RRL||}}
 +
{{rld|0x00000008|16|DDR_SEQ_TRRD||}}
 +
{{rld|0x00000009|16|DDR_SEQ_TFAW||}}
 +
{{rld|0x0000000a|16|DDR_SEQ_TRFC||}}
 +
{{rld|0x0000000b|16|DDR_SEQ_TRDWR||}}
 +
{{rld|0x0000000c|16|DDR_SEQ_TWRRD||}}
 +
{{rld|0x0000000d|16|DDR_SEQ_TR2R||}}
 +
{{rld|0x0000000e|16|DDR_SEQ_RDPR||}}
 +
{{rld|0x0000000f|16|DDR_SEQ_WRPR||}}
 +
{{rld|0x00000010|16|DDR_SEQ_BANK4||}}
 +
{{rld|0x00000011|16|DDR_SEQ_QSOE0||}}
 +
{{rld|0x00000012|16|DDR_SEQ_QSOE1||}}
 +
{{rld|0x00000013|16|DDR_SEQ_QSOE2||}}
 +
{{rld|0x00000014|16|DDR_SEQ_QSOE3||}}
 +
{{rld|0x00000015|16|DDR_SEQ_RANK2||}}
 +
{{rld|0x00000016|16|DDR_SEQ_DDR2||}}
 +
{{rld|0x00000017|16|DDR_SEQ_RSTB||}}
 +
{{rld|0x00000018|16|DDR_SEQ_CKEEN||}}
 +
{{rld|0x00000019|16|DDR_SEQ_CKEDYN||}}
 +
{{rld|0x0000001a|16|DDR_SEQ_CKESR||}}
 +
{{rld|0x0000001b|16|DDR_SEQ_ODTON||}}
 +
{{rld|0x0000001c|16|DDR_SEQ_ODTDYN||}}
 +
{{rld|0x0000001d|16|DDR_SEQ_ODT0||}}
 +
{{rld|0x0000001e|16|DDR_SEQ_ODT1||}}
 +
{{rld|0x0000001f|16|DDR_SEQ_RECEN0||}}
 +
{{rld|0x00000020|16|DDR_SEQ_RECEN1||}}
 +
{{rld|0x00000021|16|DDR_SEQ_IDLEST||}}
 +
{{rld|0x00000022|16|DDR_SEQ_NPLRD||}}
 +
{{rld|0x00000023|16|DDR_SEQ_NPLCONF||}}
 +
{{rld|0x00000024|16|DDR_SEQ_NOOPEN||}}
 +
{{rld|0x00000025|16|DDR_SEQ_QSDEF||}}
 +
{{rld|0x00000026|16|DDR_SEQ_ODTPIN||}}
 +
{{rld|0x00000027|16|DDR_SEQ_NPLDLY||}}
 +
{{rld|0x00000028|16|DDR_SEQ_STATUS||}}
 +
{{rld|0x00000029|16|DDR_SEQ_VENDORID0||}}
 +
{{rld|0x0000002a|16|DDR_SEQ_VENDORID1||}}
 +
{{rld|0x0000002b|16|DDR_SEQ_NMOSPD||}}
 +
{{rld|0x0000002c|16|DDR_SEQ_STR0||}}
 +
{{rld|0x0000002d|16|DDR_SEQ_STR1||}}
 +
{{rld|0x0000002e|16|DDR_SEQ_STR2||}}
 +
{{rld|0x0000002f|16|DDR_SEQ_STR3||}}
 +
{{rld|0x00000030|16|DDR_SEQ_APAD0||}}
 +
{{rld|0x00000031|16|DDR_SEQ_APAD1||}}
 +
{{rld|0x00000032|16|DDR_SEQ_CKPAD0||}}
 +
{{rld|0x00000033|16|DDR_SEQ_CKPAD1||}}
 +
{{rld|0x00000034|16|DDR_SEQ_CMDPAD0||}}
 +
{{rld|0x00000035|16|DDR_SEQ_CMDPAD1||}}
 +
{{rld|0x00000036|16|DDR_SEQ_DQPAD0||}}
 +
{{rld|0x00000037|16|DDR_SEQ_DQPAD1||}}
 +
{{rld|0x00000038|16|DDR_SEQ_QSPAD0||}}
 +
{{rld|0x00000039|16|DDR_SEQ_QSPAD1||}}
 +
{{rld|0x0000003a|16|DDR_SEQ_WRDQ0||}}
 +
{{rld|0x0000003b|16|DDR_SEQ_WRDQ1||}}
 +
{{rld|0x0000003c|16|DDR_SEQ_WRQS0||}}
 +
{{rld|0x0000003d|16|DDR_SEQ_WRQS1||}}
 +
{{rld|0x0000003e|16|DDR_SEQ_MADJL||}}
 +
{{rld|0x0000003f|16|DDR_SEQ_MADJH||}}
 +
{{rld|0x00000040|16|DDR_SEQ_SADJ0L||}}
 +
{{rld|0x00000041|16|DDR_SEQ_SADJ0H||}}
 +
{{rld|0x00000042|16|DDR_SEQ_SADJ1L||}}
 +
{{rld|0x00000043|16|DDR_SEQ_SADJ1H||}}
 +
{{rld|0x00000044|16|DDR_SEQ_RDDQ1||}}
 +
{{rld|0x00000045|16|DDR_SEQ_WR||}}
 +
{{rld|0x00000046|16|DDR_SEQ_PADA||}}
 +
{{rld|0x00000047|16|DDR_SEQ_PAD0||}}
 +
{{rld|0x00000048|16|DDR_SEQ_PAD1||}}
 +
{{rld|0x00000049|16|DDR_SEQ_ARAM||}}
 +
{{rld|0x0000004a|16|DDR_SEQ_WR2PR||}}
 +
{{rld|0x0000004b|16|DDR_SEQ_SYNC||}}
 +
{{rld|0x0000004c|16|DDR_SEQ_RECVON||}}
 +
|}
  
−
== DDR BIST Register Space ==
+
 
 +
= DDR BIST Register Space =
 +
{{Infobox MMIO
 +
| title = BIST
 +
| arm = Full
 +
| ppc = ???
 +
| base = N/A
 +
| len = ???
 +
| bits = 16
 +
}}
 +
''Note: These registers are NOT mapped into memory.''
 +
{{reglist|DDR BIST Registers}}
 +
{{rld|0x00000000|16|BIST_EN||}}
 +
{{rld|0x00000001|16|BIST_WRGO||}}
 +
{{rld|0x00000002|16|BIST_WRRPT||}}
 +
{{rld|0x00000003|16|BIST_WRCNTH||}}
 +
{{rld|0x00000004|16|BIST_WRCNTL||}}
 +
{{rld|0x00000005|16|BIST_RDGO||}}
 +
{{rld|0x00000006|16|BIST_RDRPT||}}
 +
{{rld|0x00000007|16|BIST_RDCNTH||}}
 +
{{rld|0x00000008|16|BIST_RDCNTL||}}
 +
{{rld|0x00000009|16|BIST_WA_CH||}}
 +
{{rld|0x0000000a|16|BIST_WA_CL||}}
 +
{{rld|0x0000000b|16|BIST_WA_SCNTH||}}
 +
{{rld|0x0000000c|16|BIST_WA_SCNTL||}}
 +
{{rld|0x0000000d|16|BIST_WA_SCONH||}}
 +
{{rld|0x0000000e|16|BIST_WA_SCONL||}}
 +
{{rld|0x0000000f|16|BIST_RA_CH||}}
 +
{{rld|0x00000010|16|BIST_RA_CL||}}
 +
{{rld|0x00000011|16|BIST_RA_SCNTH||}}
 +
{{rld|0x00000012|16|BIST_RA_SCNTL||}}
 +
{{rld|0x00000013|16|BIST_RA_SCONH||}}
 +
{{rld|0x00000014|16|BIST_RA_SCONL||}}
 +
{{rld|0x00000015|16|BIST_WD_C0H||}}
 +
{{rld|0x00000016|16|BIST_WD_C0L||}}
 +
{{rld|0x00000017|16|BIST_WD_C1H||}}
 +
{{rld|0x00000018|16|BIST_WD_C1L||}}
 +
{{rld|0x00000019|16|BIST_WD_C2H||}}
 +
{{rld|0x0000001a|16|BIST_WD_C2L||}}
 +
{{rld|0x0000001b|16|BIST_WD_C3H||}}
 +
{{rld|0x0000001c|16|BIST_WD_C3L||}}
 +
{{rld|0x0000001d|16|BIST_WD_C4H||}}
 +
{{rld|0x0000001e|16|BIST_WD_C4L||}}
 +
{{rld|0x0000001f|16|BIST_WD_C5H||}}
 +
{{rld|0x00000020|16|BIST_WD_C5L||}}
 +
{{rld|0x00000021|16|BIST_WD_C6H||}}
 +
{{rld|0x00000022|16|BIST_WD_C6L||}}
 +
{{rld|0x00000023|16|BIST_WD_C7H||}}
 +
{{rld|0x00000024|16|BIST_WD_C7L||}}
 +
{{rld|0x00000025|16|BIST_WD_SCNTH||}}
 +
{{rld|0x00000026|16|BIST_WD_SCNTL||}}
 +
{{rld|0x00000027|16|BIST_WD_SCONH||}}
 +
{{rld|0x00000028|16|BIST_WD_SCONL||}}
 +
{{rld|0x00000029|16|BIST_RD_C0H||}}
 +
{{rld|0x0000002a|16|BIST_RD_C0L||}}
 +
{{rld|0x0000002b|16|BIST_RD_C1H||}}
 +
{{rld|0x0000002c|16|BIST_RD_C1L||}}
 +
{{rld|0x0000002d|16|BIST_RD_C2H||}}
 +
{{rld|0x0000002e|16|BIST_RD_C2L||}}
 +
{{rld|0x0000002f|16|BIST_RD_C3H||}}
 +
{{rld|0x00000030|16|BIST_RD_C3L||}}
 +
{{rld|0x00000031|16|BIST_RD_C4H||}}
 +
{{rld|0x00000032|16|BIST_RD_C4L||}}
 +
{{rld|0x00000033|16|BIST_RD_C5H||}}
 +
{{rld|0x00000034|16|BIST_RD_C5L||}}
 +
{{rld|0x00000035|16|BIST_RD_C6H||}}
 +
{{rld|0x00000036|16|BIST_RD_C6L||}}
 +
{{rld|0x00000037|16|BIST_RD_C7H||}}
 +
{{rld|0x00000038|16|BIST_RD_C7L||}}
 +
{{rld|0x00000039|16|BIST_RD_SCNTH||}}
 +
{{rld|0x0000003a|16|BIST_RD_SCNTL||}}
 +
{{rld|0x0000003b|16|BIST_RD_SCONH||}}
 +
{{rld|0x0000003c|16|BIST_RD_SCONL||}}
 +
{{rld|0x0000003d|16|BIST_RD_MSKH||}}
 +
{{rld|0x0000003e|16|BIST_RD_MSKL||}}
 +
{{rld|0x0000003f|16|BIST_WRIDLE||}}
 +
{{rld|0x00000040|16|BIST_RDIDLE||}}
 +
{{rld|0x00000041|16|BIST_ERRCNT||}}
 +
|}
  
  
−
== DDR PERF Register Space ==
+
= DDR PERF Register Space =
 +
{{Infobox MMIO
 +
| title = PERF
 +
| arm = Full
 +
| ppc = ???
 +
| base = N/A
 +
| len = ???
 +
| bits = 16
 +
}}
 +
''Note: These registers are NOT mapped into memory.''
 +
{{reglist|DDR PERF Registers}}
 +
{{rld|0x00000000|16|DPERF_TIME||}}
 +
{{rld|0x00000002|16|DPERF_SEQCMD||}}
 +
{{rld|0x00000004|16|DPERF_SEQDATA||}}
 +
{{rld|0x00000006|16|DPERF_RF_CNT_PI||}}
 +
{{rld|0x00000008|16|DPERF_NREQ_DDR_PI||}}
 +
{{rld|0x0000000a|16|DPERF_TREQ_DDR_PI||}}
 +
{{rld|0x0000000c|16|DPERF_TACK_DDR_PI||}}
 +
{{rld|0x0000000e|16|DPERF_NREQ_SPL_PI||}}
 +
{{rld|0x00000010|16|DPERF_TREQ_SPL_PI||}}
 +
{{rld|0x00000012|16|DPERF_TACK_SPL_PI||}}
 +
{{rld|0x00000014|16|DPERF_RF_CNT_CPUAHM||}}
 +
{{rld|0x00000016|16|DPERF_NREQ_DDR_CPUAHM||}}
 +
{{rld|0x00000018|16|DPERF_TREQ_DDR_CPUAHM||}}
 +
{{rld|0x0000001a|16|DPERF_TACK_DDR_CPUAHM||}}
 +
{{rld|0x0000001c|16|DPERF_NREQ_SPL_CPUAHM||}}
 +
{{rld|0x0000001e|16|DPERF_TREQ_SPL_CPUAHM||}}
 +
{{rld|0x00000020|16|DPERF_TACK_SPL_CPUAHM||}}
 +
{{rld|0x00000022|16|DPERF_RF_CNT_DMAAHM||}}
 +
{{rld|0x00000024|16|DPERF_NREQ_DDR_DMAAHM||}}
 +
{{rld|0x00000026|16|DPERF_TREQ_DDR_DMAAHM||}}
 +
{{rld|0x00000028|16|DPERF_TACK_DDR_DMAAHM||}}
 +
{{rld|0x0000002a|16|DPERF_NREQ_SPL_DMAAHM||}}
 +
{{rld|0x0000002c|16|DPERF_TREQ_SPL_DMAAHM||}}
 +
{{rld|0x0000002e|16|DPERF_TACK_SPL_DMAAHM||}}
 +
{{rld|0x00000030|16|DPERF_RF_CNT_VI||}}
 +
{{rld|0x00000032|16|DPERF_NREQ_DDR_VI||}}
 +
{{rld|0x00000034|16|DPERF_TREQ_DDR_VI||}}
 +
{{rld|0x00000036|16|DPERF_TACK_DDR_VI||}}
 +
{{rld|0x00000038|16|DPERF_NREQ_SPL_VI||}}
 +
{{rld|0x0000003a|16|DPERF_TREQ_SPL_VI||}}
 +
{{rld|0x0000003c|16|DPERF_TACK_SPL_VI||}}
 +
{{rld|0x0000003e|16|DPERF_RF_CNT_IO||}}
 +
{{rld|0x00000040|16|DPERF_NREQ_DDR_IO||}}
 +
{{rld|0x00000042|16|DPERF_TREQ_DDR_IO||}}
 +
{{rld|0x00000044|16|DPERF_TACK_DDR_IO||}}
 +
{{rld|0x00000046|16|DPERF_NREQ_SPL_IO||}}
 +
{{rld|0x00000048|16|DPERF_TREQ_SPL_IO||}}
 +
{{rld|0x0000004a|16|DPERF_TACK_SPL_IO||}}
 +
{{rld|0x0000004c|16|DPERF_RF_CNT_DSP||}}
 +
{{rld|0x0000004e|16|DPERF_NREQ_DDR_DSP||}}
 +
{{rld|0x00000050|16|DPERF_TREQ_DDR_DSP||}}
 +
{{rld|0x00000052|16|DPERF_TACK_DDR_DSP||}}
 +
{{rld|0x00000054|16|DPERF_NREQ_SPL_DSP||}}
 +
{{rld|0x00000056|16|DPERF_TREQ_SPL_DSP||}}
 +
{{rld|0x00000058|16|DPERF_TACK_SPL_DSP||}}
 +
{{rld|0x0000005a|16|DPERF_RF_CNT_TC||}}
 +
{{rld|0x0000005c|16|DPERF_NREQ_DDR_TC||}}
 +
{{rld|0x0000005e|16|DPERF_TREQ_DDR_TC||}}
 +
{{rld|0x00000060|16|DPERF_TACK_DDR_TC||}}
 +
{{rld|0x00000062|16|DPERF_NREQ_SPL_TC||}}
 +
{{rld|0x00000064|16|DPERF_TREQ_SPL_TC||}}
 +
{{rld|0x00000066|16|DPERF_TACK_SPL_TC||}}
 +
{{rld|0x00000068|16|DPERF_RF_CNT_CP||}}
 +
{{rld|0x0000006a|16|DPERF_NREQ_DDR_CP||}}
 +
{{rld|0x0000006c|16|DPERF_TREQ_DDR_CP||}}
 +
{{rld|0x0000006e|16|DPERF_TACK_DDR_CP||}}
 +
{{rld|0x00000070|16|DPERF_NREQ_SPL_CP||}}
 +
{{rld|0x00000072|16|DPERF_TREQ_SPL_CP||}}
 +
{{rld|0x00000074|16|DPERF_TACK_SPL_CP||}}
 +
{{rld|0x00000076|16|DPERF_RF_CNT_ACC||}}
 +
{{rld|0x00000078|16|DPERF_NREQ_DDR_ACC||}}
 +
{{rld|0x0000007a|16|DPERF_TREQ_DDR_ACC||}}
 +
{{rld|0x0000007c|16|DPERF_TACK_DDR_ACC||}}
 +
{{rld|0x0000007e|16|DPERF_NREQ_SPL_ACC||}}
 +
{{rld|0x00000080|16|DPERF_TREQ_SPL_ACC||}}
 +
{{rld|0x00000082|16|DPERF_TACK_SPL_ACC||}}
 +
|}

Latest revision as of 06:52, 29 March 2020

Memory Controller
Access
Broadway???
StarletFull
Registers
Base0x0d8b4200
Length0xcc (?)
Access size16 bits
Byte orderBig Endian
This box: view • talk • edit


These registers contain various settings relevant to configuring system memory (and perhaps some aspects of the AHB). boot1 seems responsible for initially configuring a lot of these registers during the boot process - most likely for setting the DDR memory timings. In general, IOS (including BC/MIOS) seem to interact with these early when booting. The IOS[58] kernel also exposes syscall 0x57 for writing to this register space, which only appears to be used by the STM module.

Some of these register banks (SEQ/BIST/PERF) are not directly mapped into memory, but are instead accessed using a corresponding pair of registers:

  • For the DDR SEQ registers, MEM_SEQ_ADDR and MEM_SEQ_DATA
  • For the DDR BIST, MEM_BIST_ADDR and MEM_BIST_DATA
  • For the DPERF registers, presumably MEM_PERF and MEM_PERF_READ are involved [check]
  • MEM_ARB_EXADDR and MEM_ARB_EXCMD are used during DRAM initialization for Mode Register Set programming (the layout is probably vendor-specific).

Although the memory controller registers are actually mapped and available to ARM starting at 0x0d8b4200, some [all?] of the indirect accesses are performed starting with another pair in the Memory Interface registers.


Memory Controller Base Registers
Address Bits Name Description
0x0d8b4200 16 MEM_COMPAT
0x0d8b4202 16 MEM_PROT_REG
0x0d8b4204 16 MEM_PROT_SPL SPL (?) protection enabled/disable
0x0d8b4206 16 MEM_PROT_SPL_BASE SPL (?) protection base address
0x0d8b4208 16 MEM_PROT_SPL_END SPL (?) protection end address
0x0d8b420a 16 MEM_PROT_DDR DDR protection enable/disable
0x0d8b420c 16 MEM_PROT_DDR_BASE DDR protection base address
0x0d8b420e 16 MEM_PROT_DDR_END DDR protection end address
0x0d8b4210 16 MEM_COLSEL
0x0d8b4212 16 MEM_ROWSEL
0x0d8b4214 16 MEM_BANKSEL
0x0d8b4216 16 MEM_RANKSEL
0x0d8b4218 16 MEM_COLMSK
0x0d8b421a 16 MEM_ROWMSK
0x0d8b421c 16 MEM_BANKMSK
0x0d8b421e 16 MEM_PROT_SPL_ERR
0x0d8b4220 16 MEM_PROT_DDR_ERR
0x0d8b4222 16 MEM_PROT_SPL_MSK
0x0d8b4224 16 MEM_PROT_DDR_MSK
0x0d8b4226 16 MEM_RFSH
0x0d8b4228 16 MEM_AHMFLUSH AHB flush request
0x0d8b422a 16 MEM_AHMFLUSH_ACK AHB flush request acknowledgment
0x0d8b4268 16 MEM_SEQRD_HWM
0x0d8b426a 16 MEM_SEQWR_HWM
0x0d8b426c 16 MEM_SEQCMD_HWM
0x0d8b426e 16 MEM_CPUAHM_WR_T
0x0d8b4270 16 MEM_DMAAHM_WR_T
0x0d8b4272 16 MEM_DMAAHM0_WR_T
0x0d8b4274 16 MEM_DMAAHM1_WR_T
0x0d8b4276 16 MEM_PI_WR_T
0x0d8b4278 16 MEM_PE_WR_T
0x0d8b427a 16 MEM_IO_WR_T
0x0d8b427c 16 MEM_DSP_WR_T
0x0d8b427e 16 MEM_ACC_WR_T
0x0d8b4280 16 MEM_ARB_MAXWR
0x0d8b4282 16 MEM_ARB_MINRD
0x0d8b4284 16 MEM_PROF_CPUAHM
0x0d8b4286 16 MEM_PROF_CPUAHM0
0x0d8b4288 16 MEM_PROF_DMAAHM
0x0d8b428a 16 MEM_PROF_DMAAHM0
0x0d8b428c 16 MEM_PROF_DMAAHM1
0x0d8b428e 16 MEM_PROF_PI
0x0d8b4290 16 MEM_PROF_VI
0x0d8b4292 16 MEM_PROF_IO
0x0d8b4294 16 MEM_PROF_DSP
0x0d8b4296 16 MEM_PROF_TC
0x0d8b4298 16 MEM_PROF_CP
0x0d8b429a 16 MEM_PROF_ACC
0x0d8b429c 16 MEM_RDPR_CPUAHM
0x0d8b429e 16 MEM_RDPR_CPUAHM0
0x0d8b42a0 16 MEM_RDPR_DMAAHM
0x0d8b42a2 16 MEM_RDPR_DMAAHM0
0x0d8b42a4 16 MEM_RDPR_DMAAHM1
0x0d8b42a6 16 MEM_RDPR_PI
0x0d8b42a8 16 MEM_RDPR_VI
0x0d8b42aa 16 MEM_RDPR_IO
0x0d8b42ac 16 MEM_RDPR_DSP
0x0d8b42ae 16 MEM_RDPR_TC
0x0d8b42b0 16 MEM_RDPR_CP
0x0d8b42b2 16 MEM_RDPR_ACC
0x0d8b42b4 16 MEM_ARB_MAXRD
0x0d8b42b6 16 MEM_ARB_MISC
0x0d8b42b8 16 MEM_ARAM_EMUL "ARAM Emulation" (?)
0x0d8b42ba 16 MEM_WRMUX
0x0d8b42bc 16 MEM_PERF
0x0d8b42be 16 MEM_PERF_READ
0x0d8b42c0 16 MEM_ARB_EXADDR
0x0d8b42c2 16 MEM_ARB_EXCMD
0x0d8b42c4 16 MEM_SEQ_DATA Data from read (or for pending write) on DDR SEQ
0x0d8b42c6 16 MEM_SEQ_ADDR Offset for access on DDR SEQ register space
0x0d8b42c8 16 MEM_BIST_DATA Data from read (or for pending write) on DDR BIST
0x0d8b42ca 16 MEM_BIST_ADDR Offset for access on DDR BIST register space

DDR SEQ Register Space

SEQ
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
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Note: These registers are NOT mapped into memory.

DDR SEQ Registers
Address Bits Name Description


0x00000000 16 DDR_SEQ_BL4
0x00000001 16 DDR_SEQ_TRCDR
0x00000002 16 DDR_SEQ_TRCDW
0x00000003 16 DDR_SEQ_TRAS
0x00000004 16 DDR_SEQ_TRC
0x00000005 16 DDR_SEQ_TCL
0x00000006 16 DDR_SEQ_TWL
0x00000007 16 DDR_SEQ_RRL
0x00000008 16 DDR_SEQ_TRRD
0x00000009 16 DDR_SEQ_TFAW
0x0000000a 16 DDR_SEQ_TRFC
0x0000000b 16 DDR_SEQ_TRDWR
0x0000000c 16 DDR_SEQ_TWRRD
0x0000000d 16 DDR_SEQ_TR2R
0x0000000e 16 DDR_SEQ_RDPR
0x0000000f 16 DDR_SEQ_WRPR
0x00000010 16 DDR_SEQ_BANK4
0x00000011 16 DDR_SEQ_QSOE0
0x00000012 16 DDR_SEQ_QSOE1
0x00000013 16 DDR_SEQ_QSOE2
0x00000014 16 DDR_SEQ_QSOE3
0x00000015 16 DDR_SEQ_RANK2
0x00000016 16 DDR_SEQ_DDR2
0x00000017 16 DDR_SEQ_RSTB
0x00000018 16 DDR_SEQ_CKEEN
0x00000019 16 DDR_SEQ_CKEDYN
0x0000001a 16 DDR_SEQ_CKESR
0x0000001b 16 DDR_SEQ_ODTON
0x0000001c 16 DDR_SEQ_ODTDYN
0x0000001d 16 DDR_SEQ_ODT0
0x0000001e 16 DDR_SEQ_ODT1
0x0000001f 16 DDR_SEQ_RECEN0
0x00000020 16 DDR_SEQ_RECEN1
0x00000021 16 DDR_SEQ_IDLEST
0x00000022 16 DDR_SEQ_NPLRD
0x00000023 16 DDR_SEQ_NPLCONF
0x00000024 16 DDR_SEQ_NOOPEN
0x00000025 16 DDR_SEQ_QSDEF
0x00000026 16 DDR_SEQ_ODTPIN
0x00000027 16 DDR_SEQ_NPLDLY
0x00000028 16 DDR_SEQ_STATUS
0x00000029 16 DDR_SEQ_VENDORID0
0x0000002a 16 DDR_SEQ_VENDORID1
0x0000002b 16 DDR_SEQ_NMOSPD
0x0000002c 16 DDR_SEQ_STR0
0x0000002d 16 DDR_SEQ_STR1
0x0000002e 16 DDR_SEQ_STR2
0x0000002f 16 DDR_SEQ_STR3
0x00000030 16 DDR_SEQ_APAD0
0x00000031 16 DDR_SEQ_APAD1
0x00000032 16 DDR_SEQ_CKPAD0
0x00000033 16 DDR_SEQ_CKPAD1
0x00000034 16 DDR_SEQ_CMDPAD0
0x00000035 16 DDR_SEQ_CMDPAD1
0x00000036 16 DDR_SEQ_DQPAD0
0x00000037 16 DDR_SEQ_DQPAD1
0x00000038 16 DDR_SEQ_QSPAD0
0x00000039 16 DDR_SEQ_QSPAD1
0x0000003a 16 DDR_SEQ_WRDQ0
0x0000003b 16 DDR_SEQ_WRDQ1
0x0000003c 16 DDR_SEQ_WRQS0
0x0000003d 16 DDR_SEQ_WRQS1
0x0000003e 16 DDR_SEQ_MADJL
0x0000003f 16 DDR_SEQ_MADJH
0x00000040 16 DDR_SEQ_SADJ0L
0x00000041 16 DDR_SEQ_SADJ0H
0x00000042 16 DDR_SEQ_SADJ1L
0x00000043 16 DDR_SEQ_SADJ1H
0x00000044 16 DDR_SEQ_RDDQ1
0x00000045 16 DDR_SEQ_WR
0x00000046 16 DDR_SEQ_PADA
0x00000047 16 DDR_SEQ_PAD0
0x00000048 16 DDR_SEQ_PAD1
0x00000049 16 DDR_SEQ_ARAM
0x0000004a 16 DDR_SEQ_WR2PR
0x0000004b 16 DDR_SEQ_SYNC
0x0000004c 16 DDR_SEQ_RECVON


DDR BIST Register Space

BIST
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
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Note: These registers are NOT mapped into memory.

DDR BIST Registers
Address Bits Name Description
0x00000000 16 BIST_EN
0x00000001 16 BIST_WRGO
0x00000002 16 BIST_WRRPT
0x00000003 16 BIST_WRCNTH
0x00000004 16 BIST_WRCNTL
0x00000005 16 BIST_RDGO
0x00000006 16 BIST_RDRPT
0x00000007 16 BIST_RDCNTH
0x00000008 16 BIST_RDCNTL
0x00000009 16 BIST_WA_CH
0x0000000a 16 BIST_WA_CL
0x0000000b 16 BIST_WA_SCNTH
0x0000000c 16 BIST_WA_SCNTL
0x0000000d 16 BIST_WA_SCONH
0x0000000e 16 BIST_WA_SCONL
0x0000000f 16 BIST_RA_CH
0x00000010 16 BIST_RA_CL
0x00000011 16 BIST_RA_SCNTH
0x00000012 16 BIST_RA_SCNTL
0x00000013 16 BIST_RA_SCONH
0x00000014 16 BIST_RA_SCONL
0x00000015 16 BIST_WD_C0H
0x00000016 16 BIST_WD_C0L
0x00000017 16 BIST_WD_C1H
0x00000018 16 BIST_WD_C1L
0x00000019 16 BIST_WD_C2H
0x0000001a 16 BIST_WD_C2L
0x0000001b 16 BIST_WD_C3H
0x0000001c 16 BIST_WD_C3L
0x0000001d 16 BIST_WD_C4H
0x0000001e 16 BIST_WD_C4L
0x0000001f 16 BIST_WD_C5H
0x00000020 16 BIST_WD_C5L
0x00000021 16 BIST_WD_C6H
0x00000022 16 BIST_WD_C6L
0x00000023 16 BIST_WD_C7H
0x00000024 16 BIST_WD_C7L
0x00000025 16 BIST_WD_SCNTH
0x00000026 16 BIST_WD_SCNTL
0x00000027 16 BIST_WD_SCONH
0x00000028 16 BIST_WD_SCONL
0x00000029 16 BIST_RD_C0H
0x0000002a 16 BIST_RD_C0L
0x0000002b 16 BIST_RD_C1H
0x0000002c 16 BIST_RD_C1L
0x0000002d 16 BIST_RD_C2H
0x0000002e 16 BIST_RD_C2L
0x0000002f 16 BIST_RD_C3H
0x00000030 16 BIST_RD_C3L
0x00000031 16 BIST_RD_C4H
0x00000032 16 BIST_RD_C4L
0x00000033 16 BIST_RD_C5H
0x00000034 16 BIST_RD_C5L
0x00000035 16 BIST_RD_C6H
0x00000036 16 BIST_RD_C6L
0x00000037 16 BIST_RD_C7H
0x00000038 16 BIST_RD_C7L
0x00000039 16 BIST_RD_SCNTH
0x0000003a 16 BIST_RD_SCNTL
0x0000003b 16 BIST_RD_SCONH
0x0000003c 16 BIST_RD_SCONL
0x0000003d 16 BIST_RD_MSKH
0x0000003e 16 BIST_RD_MSKL
0x0000003f 16 BIST_WRIDLE
0x00000040 16 BIST_RDIDLE
0x00000041 16 BIST_ERRCNT


DDR PERF Register Space

PERF
Access
Broadway???
StarletFull
Registers
BaseN/A
Length???
Access size16 bits
Byte orderBig Endian
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Note: These registers are NOT mapped into memory.

DDR PERF Registers
Address Bits Name Description
0x00000000 16 DPERF_TIME
0x00000002 16 DPERF_SEQCMD
0x00000004 16 DPERF_SEQDATA
0x00000006 16 DPERF_RF_CNT_PI
0x00000008 16 DPERF_NREQ_DDR_PI
0x0000000a 16 DPERF_TREQ_DDR_PI
0x0000000c 16 DPERF_TACK_DDR_PI
0x0000000e 16 DPERF_NREQ_SPL_PI
0x00000010 16 DPERF_TREQ_SPL_PI
0x00000012 16 DPERF_TACK_SPL_PI
0x00000014 16 DPERF_RF_CNT_CPUAHM
0x00000016 16 DPERF_NREQ_DDR_CPUAHM
0x00000018 16 DPERF_TREQ_DDR_CPUAHM
0x0000001a 16 DPERF_TACK_DDR_CPUAHM
0x0000001c 16 DPERF_NREQ_SPL_CPUAHM
0x0000001e 16 DPERF_TREQ_SPL_CPUAHM
0x00000020 16 DPERF_TACK_SPL_CPUAHM
0x00000022 16 DPERF_RF_CNT_DMAAHM
0x00000024 16 DPERF_NREQ_DDR_DMAAHM
0x00000026 16 DPERF_TREQ_DDR_DMAAHM
0x00000028 16 DPERF_TACK_DDR_DMAAHM
0x0000002a 16 DPERF_NREQ_SPL_DMAAHM
0x0000002c 16 DPERF_TREQ_SPL_DMAAHM
0x0000002e 16 DPERF_TACK_SPL_DMAAHM
0x00000030 16 DPERF_RF_CNT_VI
0x00000032 16 DPERF_NREQ_DDR_VI
0x00000034 16 DPERF_TREQ_DDR_VI
0x00000036 16 DPERF_TACK_DDR_VI
0x00000038 16 DPERF_NREQ_SPL_VI
0x0000003a 16 DPERF_TREQ_SPL_VI
0x0000003c 16 DPERF_TACK_SPL_VI
0x0000003e 16 DPERF_RF_CNT_IO
0x00000040 16 DPERF_NREQ_DDR_IO
0x00000042 16 DPERF_TREQ_DDR_IO
0x00000044 16 DPERF_TACK_DDR_IO
0x00000046 16 DPERF_NREQ_SPL_IO
0x00000048 16 DPERF_TREQ_SPL_IO
0x0000004a 16 DPERF_TACK_SPL_IO
0x0000004c 16 DPERF_RF_CNT_DSP
0x0000004e 16 DPERF_NREQ_DDR_DSP
0x00000050 16 DPERF_TREQ_DDR_DSP
0x00000052 16 DPERF_TACK_DDR_DSP
0x00000054 16 DPERF_NREQ_SPL_DSP
0x00000056 16 DPERF_TREQ_SPL_DSP
0x00000058 16 DPERF_TACK_SPL_DSP
0x0000005a 16 DPERF_RF_CNT_TC
0x0000005c 16 DPERF_NREQ_DDR_TC
0x0000005e 16 DPERF_TREQ_DDR_TC
0x00000060 16 DPERF_TACK_DDR_TC
0x00000062 16 DPERF_NREQ_SPL_TC
0x00000064 16 DPERF_TREQ_SPL_TC
0x00000066 16 DPERF_TACK_SPL_TC
0x00000068 16 DPERF_RF_CNT_CP
0x0000006a 16 DPERF_NREQ_DDR_CP
0x0000006c 16 DPERF_TREQ_DDR_CP
0x0000006e 16 DPERF_TACK_DDR_CP
0x00000070 16 DPERF_NREQ_SPL_CP
0x00000072 16 DPERF_TREQ_SPL_CP
0x00000074 16 DPERF_TACK_SPL_CP
0x00000076 16 DPERF_RF_CNT_ACC
0x00000078 16 DPERF_NREQ_DDR_ACC
0x0000007a 16 DPERF_TREQ_DDR_ACC
0x0000007c 16 DPERF_TACK_DDR_ACC
0x0000007e 16 DPERF_NREQ_SPL_ACC
0x00000080 16 DPERF_TREQ_SPL_ACC
0x00000082 16 DPERF_TACK_SPL_ACC
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