Line 9:
Line 9:
== Register List ==
== Register List ==
−
{{reglist|NAND Interface}}
+
{{reglist|AES Engine}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}