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2,900 bytes added ,  23:40, 22 October 2008
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This page lists the known Starlet I/O registers.  Much of this info comes from Segher & tmbinc's private notes.
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This page lists the known [[Starlet]] I/O registers.  Much of this info comes from Segher & tmbinc's private notes.
    
== Memory map ==
 
== Memory map ==
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{| class="wikitable"
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{| style="border-collapse: collapse; padding: 0.2em 0.2em 0.2em 0.2em;"
|-
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|- style="background-color: #ddd;"
! Start Address
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Start Address'''
! End Address
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''End Address'''
! Physical Address
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Physical Address'''
! Size
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Size'''
! Description
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #ddd;" | '''Description'''
|-
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| 0x00000000
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|- style="background-color: #ddd;"
| 0x017FFFFF
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
| 0x00000000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x017FFFFF
| 24 MB
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x00000000
| MEM1 Memory (Cached)
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 24 MB
|-
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM1 Memory (Cached)
| 0x10000000
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| 0x13FFFFFF
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|- style="background-color: #ddd;"
| 0x10000000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
| 64 MB
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x13FFFFFF
| MEM2 Memory (Cached)
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x10000000
|-
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 64 MB
| 0x0D000000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | MEM2 Memory (Cached)
|  
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| 0x0D000000
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|- style="background-color: #ddd;"
|  
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D000000
| Hardware Registers (shared with the Broadway)
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
|-
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D000000
| 0x0D400000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |  
|  
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers (shared with the Broadway)
| 0x0D400000
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|  
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|- style="background-color: #ddd;"
| RAM used for program code, data and stack
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D400000
|-
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
| 0x0D800000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D400000
|  
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |  
| 0x0D800000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | RAM used for program code, data and stack
|  
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| Hardware Registers (Starlet private)
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|- style="background-color: #ddd;"
|-
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D800000
| 0xFFFE0000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |
| 0xFFFFFFFF
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0x0D800000
|  
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |  
|  
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Hardware Registers (Starlet private)
| Internal SRAM
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|- style="background-color: #ddd;"
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xFFFE0000
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | 0xFFFFFFFF
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| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |  
 +
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" |  
 +
| style="border: 1px solid #ccc; padding: 0.2em; background-color: #dde;" | Internal SRAM
 
|}
 
|}
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== IO Memory ==
 
== IO Memory ==
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{| border="1"
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{| border=1
! base      !! function !! offset !! description !! contents/example
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| base      || function || offset || description || contents/example
 
|-
 
|-
 
|0x0D010000||NAND      ||  
 
|0x0D010000||NAND      ||  
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