5,579
edits
Changes
m
Hallowizer moved page Hardware/AES Engine to Hardware/AES engine: Sentence case
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Set the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.+
== Register List ==
== Register List ==
−{{reglist|NAND Interface}}
+{{reglist|AES Engine}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}
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|}
|}
== Register Details ==
== Register Details ==
−{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 4 |
+{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 3 |
−|1|1|1|1|1|7|
+|1|1|1|1|1|11|
−|R/W|R/W|R?|R/W|R/W|U|
+|R/W|R/W|R/W|R/W|R/W|U|
−|EXEC|IRQ|ERR|CMD|MODE|||
+|EXEC|IRQ|ERR|ENA|DEC|||
|3|1|12|
|3|1|12|
|U|W|W|
|U|W|W|
−||IV||BLOCKS|
+||IV|BLOCKS|
}}
}}
This register controls the state of the AES engine.
This register controls the state of the AES engine.
{{regdesc
{{regdesc
−|EXEC|Write 1: initiate AES command<br/>Read: AES engine busy
+|EXEC|Write 1: initiate AES command<br/>Write 0: reset AES engine<br/>Read: AES engine busy
|IRQ|Set to enable IRQ generation when command is complete
|IRQ|Set to enable IRQ generation when command is complete
−|ERR|If set, AES error occured (?){{check}}
+|ERR|If set, AES error occurred (?){{check}}
|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).
|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).
−|MODE|0 for encrypt, 1 for decrypt.
+|DEC|Set to decrypt, clear to encrypt
−|IV|If set, use the supplied IV. If clear, chain from last command (continue CBC mode).
+|IV|If set, chain from last command (continue CBC mode). If clear, use the supplied IV.
|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.
|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.
}}
}}
----
----
−{{regsimple | AES_SRC | addr = 0x0d020004 | bits = 32 | access = R/W }}
+{{regsimple2 | AES_SRC | addr = 0x0d020004 | bits = 32 | split=4 | access = U | accesshi = R/W }}
−This register contains the DMA address of the source data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
+This register contains the DMA address of the source data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
+The engine updates this register as it processes the blocks.
----
----
−{{regsimple | AES_SRC | addr = 0x0d020008 | bits = 32 | access = R/W }}
+{{regsimple2 | AES_DEST | addr = 0x0d020008 | bits = 32 | split=4 | access = U | accesshi = R/W}}
−This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The bottom 4 bits are ignored (must be 16-byte aligned).
+This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
+The engine updates this register as it processes the blocks.
----
----
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
----
----
−{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
+{{regsimple | AES_IV | addr = 0x0d020010 | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).
−Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.