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Hallowizer moved page Hardware/AES Engine to Hardware/AES engine: Sentence case
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{| border="1"+! base !! function !! offset !! description !! contents/example+
−|-||0x0D020000||AES ||+|-+|| || || 0000 W || command || 980000LL to start operation (L = len in 16 byte blocks -1)+|| || || 0000 R || status || MSB means busy
−|-
−|| || || 0008 W || data addr|| dst DMA
−|-
−|| || || 000C W || key fifo || write 4 words to set key
−|-
−|| || || 0010 W || IV fifo || write 4 words to set IV
| hwdirq = 2
| hwdirq = 2
}}
}}
−The Hollywood's AES Engine encrypts/decrypts 16-byte blocks using AES-128 in Cipher Block Chaining mode.
−== Register List ==
−{{reglist|AES Engine}}
−{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
−|-
+{{rla|0x0d020004|32|AES_SRC|Source memory address}}
−|| || || || || 980010LL start operation and "do not reload IV"??
+{{rla|0x0d020008|32|AES_DEST|Destination memory address}}
−|-
+{{rla|0x0d02000c|32|AES_KEY|Key FIFO}}
−|| || || || || 00000000 reset
+{{rla|0x0d020010|32|AES_IV|IV FIFO}}
−|-
−|| || || 0004 W || data addr || source DMA
−|-
−|}
|}
+== Register Details ==
+{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 3 |
+|1|1|1|1|1|11|
+|R/W|R/W|R/W|R/W|R/W|U|
+|EXEC|IRQ|ERR|ENA|DEC|||
+|3|1|12|
+|U|W|W|
+||IV|BLOCKS|
+}}
+This register controls the state of the AES engine.
+{{regdesc
+|EXEC|Write 1: initiate AES command<br/>Write 0: reset AES engine<br/>Read: AES engine busy
+|IRQ|Set to enable IRQ generation when command is complete
+|ERR|If set, AES error occurred (?){{check}}
+|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).
+|DEC|Set to decrypt, clear to encrypt
+|IV|If set, chain from last command (continue CBC mode). If clear, use the supplied IV.
+|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.
+}}
+----
+{{regsimple2 | AES_SRC | addr = 0x0d020004 | bits = 32 | split=4 | access = U | accesshi = R/W }}
+This register contains the DMA address of the source data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
+The engine updates this register as it processes the blocks.
+----
+{{regsimple2 | AES_DEST | addr = 0x0d020008 | bits = 32 | split=4 | access = U | accesshi = R/W}}
+This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
+The engine updates this register as it processes the blocks.
+----
+{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
+This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
+----
+{{regsimple | AES_IV | addr = 0x0d020010 | bits = 32 | access = W }}
+This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).
+Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.