324
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Changes
Hardware/Processor Interface (view source)
Revision as of 04:20, 18 October 2012
, 04:20, 18 October 2012clarify PI_FIFO_WP
Line 91:
Line 91:
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−{{regsimple | PI_FIFO_WP | addr=0xCC003014 | bits=32 | access = R/W}}
+{{reg32 | PI_FIFO_WP | addr = 0x0C003014 | hifields = 3 | lofields = 2 |
+|2 |1 | 13 |
+|U |R |R/W |
+| |WRAPPED|ADDR ||
+|11 |5 |
+|R/W |U |
+|ADDR | |
+}}
+This register holds the current address and state of the CPU FIFO write pointer.
+{{regdesc
+|WRAPPED|Indicates the write pointer reached the end of the FIFO and wrapped to the start. Note that it is in a different location from the gamecube to allow for MEM2 addresses.
+|ADDR|Word address that will be written to next.
+}}