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Hardware/Processor Interface (view source)
Revision as of 04:20, 18 October 2012
, 04:20, 18 October 2012clarify PI_FIFO_WP
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{{Infobox MMIO
{{Infobox MMIO
| ppc = Full
| ppc = Full
−| base = 0xcc003000
+| base = 0x0c003000
| len = 0x100
| len = 0x100
| bits = 32
| bits = 32
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{{yagcd}}
{{yagcd}}
−==Interrupt Cause (0xCC003000)==
+==Interrupt Cause (0x0C003000)==
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
|- style="background-color: #ddd;"
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Line 52:
|}
|}
−==Interrupt Mask (0xCC003004)==
+==Interrupt Mask (0x0C003004)==
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
|- style="background-color: #ddd;"
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| 15-31 || Unused/reserved
| 15-31 || Unused/reserved
|}
|}
+
+{{reg32 | PI_FIFO_WP | addr = 0x0C003014 | hifields = 3 | lofields = 2 |
+|2 |1 | 13 |
+|U |R |R/W |
+| |WRAPPED|ADDR ||
+|11 |5 |
+|R/W |U |
+|ADDR | |
+}}
+This register holds the current address and state of the CPU FIFO write pointer.
+{{regdesc
+|WRAPPED|Indicates the write pointer reached the end of the FIFO and wrapped to the start. Note that it is in a different location from the gamecube to allow for MEM2 addresses.
+|ADDR|Word address that will be written to next.
+}}